| Class 716 | COMPUTER-AIDED DESIGN AND ANALYSIS OF CIRCUITS AND SEMICONDUCTOR MASKS |
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![[List of Pre Grant Publications for class 716 subclass 30]](../as.gif) | ![[List of Patents for class 716 subclass 30]](../ps.gif) | 30 | NANOTECHNOLOGY RELATED INTEGRATED CIRCUIT DESIGN |
| | 50 | DESIGN OF SEMICONDUCTOR MASK OR RETICLE |
| | 51 |  Analysis and verification (process flow, inspection) |
| | 54 | Manufacturing optimizations |
| | 55 | Layout generation (polygon, pattern feature) |
| | 56 | Yield |
| | 100 | INTEGRATED CIRCUIT DESIGN PROCESSING |
| | 101 | Logic design processing |
| | 102 |  Design entry |
| | 103 | Translation (logic-to-logic, logic-to-netlist, netlist processing) |
| | 104 | Logic circuit synthesis (mapping logic) |
| | 106 | Design verification (functional simulation, model checking) |
| | 110 | Physical design processing |
| | 111 | Verification |
| | 116 | Mapping circuit design to programmable logic devices (PLDs) |
| | 118 | Floorplanning |
| | 126 | Routing |
| | 132 | Optimization |
| | 136 | Testing or Evaluating |
| | 137 | PCB, MCM Design |
| | 138 | System-on-chip design |
| | 139 | Layout editor (with ECO, reuse, GUI) |
| FOREIGN ART COLLECTIONS | ||
| FOR000 | CLASS-RELATED FOREIGN DOCUMENTS |
| Any foreign patents or non-patent literature from subclasses that have been reclassified have been transferred directly to FOR Collections listed below. These Collections contain ONLY foreign patents or non-patent literature. The parenthetical references in the Collection titles refer to the abolished subclasses from which these Collections were derived. | ||
| FOR100 | CIRCUIT DESIGN (716/1) |
| FOR101 | Optimization (e.g., redundancy, compaction) (716/2) |
| FOR102 | Translation (e.g., conversion, equivalence) (716/3) |
| FOR103 | Testing or evaluating (716/4) |
| FOR104 | Design verification (e.g., wiring line capacitance, fanout checking, minimum path width) (716/5) |
| FOR106 | Partitioning (e.g., function block, ordering constraint) (716/7) |
| FOR107 | Floorplanning (716/8) |
| FOR108 | Detailed placement (i.e., iterative improvement) (716/9) |
| FOR109 | Constraint-based placement (e.g., critical block assignment, delay limits, wiring capacitance) (716/10) |
| FOR110 | Layout editor (e.g., updating) (716/11) |
| FOR111 | Routing (e.g., routing map, netlisting) (716/12) |
| FOR112 | Global routing (e.g., shortest path, dead space, or duplicate trace elimination) (716/13) |
| FOR113 | Detailed routing (e.g., channel routing, switch box routing( (716/14) |
| FOR114 | PCB wiring (716/15) |
| FOR115 | PLA, PLD, FPGA, OR MCM (716/16) |
| FOR116 | Programmable integrated circuit (e.g., basic cell, standard cell, macrocell) (716/17) |
| FOR117 | Logical circuit synthesizer (716/18) |
| FOR118 | DESIGN OF SEMICONDUCTOR MASK (716/19) |
| APPLICATIONS (364/400) |