| Class 257 | ACTIVE SOLID-STATE DEVICES (E.G., TRANSISTORS, SOLID-STATE DIODES) |
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| When placing a mandatory classification in Class 257, a cross-reference classification is normally made in at least one of the appended E-subclasses. | ||
![[List of Pre Grant Publications for class 257 subclass 1]](../as.gif) | ![[List of Patents for class 257 subclass 1]](../ps.gif) | 1 | BULK EFFECT DEVICE |
| | 2 |  Bulk effect switching in amorphous material |
| | 3 |  With means to localize region of conduction (e.g., "pore" structure) |
| | 4 | With specified electrode composition or configuration |
| | 5 | In array |
| | 6 | Intervalley transfer (e.g., Gunn effect) |
| | 9 | THIN ACTIVE PHYSICAL LAYER WHICH IS (1) AN ACTIVE POTENTIAL WELL LAYER THIN ENOUGH TO ESTABLISH DISCRETE QUANTUM ENERGY LEVELS OR (2) AN ACTIVE BARRIER LAYER THIN ENOUGH TO PERMIT QUANTUM MECHANICAL TUNNELING OR (3) AN ACTIVE LAYER THIN ENOUGH TO PERMIT CARRIER TRANSMISSION WITH SUBSTANTIALLY NO SCATTERING (E.G., SUPERLATTICE QUANTUM WELL, OR BALLISTIC TRANSPORT DEVICE) |
| | 10 | Low workfunction layer for electron emission (e.g., photocathode electron emissive layer) |
| | 12 | Heterojunction |
| | 13 | Incoherent light emitter |
| | 14 | Quantum well |
| | 15 |  Superlattice |
| | 16 |  Of amorphous semiconductor material |
| | 17 | With particular barrier dimension |
| | 18 | Strained layer superlattice |
| | 20 | Field effect device |
| | 21 | Light responsive structure |
| | 22 | With specified semiconductor materials |
| | 23 | Current flow across well |
| | 24 | Field effect device |
| | 25 | Employing resonant tunneling |
| | 26 | Ballistic transport device |
| | 28 | Non-heterojunction superlattice (e.g., doping superlattice or alternating metal and insulator layers) |
| | 29 | Ballistic transport device (e.g., hot electron transistor) |
| | 30 | Tunneling through region of reduced conductivity |
| | 31 | Josephson |
| | 32 | Particular electrode material |
| | 34 | Weak link (e.g., narrowed portion of superconductive line) |
| | 35 | Particular barrier material |
| | 36 | With additional electrode to control conductive state of Josephson junction |
| | 37 | At least one electrode layer of semiconductor material |
| | 39 | Three or more electrode device |
| | 40 | ORGANIC SEMICONDUCTOR MATERIAL |
| | 41 | POINT CONTACT DEVICE |
| | 42 | SEMICONDUCTOR IS SELENIUM OR TELLURIUM IN ELEMENTAL FORM |
| | 43 | SEMICONDUCTOR IS AN OXIDE OF A METAL (E.G., CUO, ZNO) OR COPPER SULFIDE |
| | 44 | WITH METAL CONTACT ALLOYED TO ELEMENTAL SEMICONDUCTOR TYPE PN JUNCTION IN NONREGENERATIVE STRUCTURE |
| | 45 | Elongated alloyed region (e.g., thermal gradient zone melting, TGZM) |
| | 46 | In pn junction tunnel diode (Esaki diode) |
| | 47 | In bipolar transistor structure |
| | 48 | TEST OR CALIBRATION STRUCTURE |
| | 49 | NON-SINGLE CRYSTAL, OR RECRYSTALLIZED, SEMICONDUCTOR MATERIAL FORMS PART OF ACTIVE JUNCTION (INCLUDING FIELD-INDUCED ACTIVE JUNCTION) |
| | 50 | Non-single crystal, or recrystallized, active junction adapted to be electrically shorted (e.g., "anti-fuse" element) |
| | 51 | Non-single crystal, or recrystallized, material forms active junction with single crystal material (e.g., monocrystal to polycrystal pn junction or heterojunction) |
| | 52 | Amorphous semiconductor material |
| | 53 | Responsive to nonelectrical external signals (e.g., light) |
| | 54 | With Schottky barrier to amorphous material |
| | 55 | Amorphous semiconductor is alloy or contains material to change band gap (e.g., Si x Ge 1-x , SiN y ) |
| | 56 | With impurity other than hydrogen to passivate dangling bonds (e.g., halide) |
| | 57 | Field effect device in amorphous semiconductor material |
| | 58 | With impurity other than hydrogen to passivate dangling bonds (e.g., halide) |
| | 59 | In array having structure for use as imager or display, or with transparent electrode |
| | 60 | With field electrode under or on a side edge of amorphous semiconductor material (e.g., vertical current path) |
| | 61 | With heavily doped regions contacting amorphous semiconductor material (e.g., heavily doped source and drain) |
| | 62 | With impurity other than hydrogen to passivate dangling bonds (e.g., halide) |
| | 63 | Amorphous semiconductor is alloy or contains material to change band gap (e.g., Si x Ge 1-x , SiN y ) |
| | 64 | Non-single crystal, or recrystallized, material with specified crystal structure (e.g., specified crystal size or orientation) |
| | 65 | Non-single crystal, or recrystallized, material containing non-dopant additive, or alloy of semiconductor materials (e.g., Ge x Si 1- x, polycrystalline silicon with dangling bond modifier) |
| | 66 | Field effect device in non-single crystal, or recrystallized, Semiconductor material |
| | 67 | In combination with device formed in single crystal semiconductor material (e.g., stacked FETs) |
| | 68 | Capacitor element in single crystal semiconductor (e.g., DRAM) |
| | 69 | Field effect transistor in single crystal material, complementary to that in non-single crystal, or recrystallized, material (e.g., CMOS) |
| | 70 | Recrystallized semiconductor material |
| | 71 | In combination with capacitor element (e.g., DRAM) |
| | 72 | In array having structure for use as imager or display, or with transparent electrode |
| | 73 | Schottky barrier to polycrystalline semiconductor material |
| | 74 | Plural recrystallized semiconductor layers (e.g., "3-dimensional integrated circuit") |
| | 75 | Recrystallized semiconductor material |
| | 76 | SPECIFIED WIDE BAND GAP (1.5EV) SEMICONDUCTOR MATERIAL OTHER THAN GAASP OR GAALAS |
| | 79 | INCOHERENT LIGHT EMITTER STRUCTURE |
| | 80 | In combination with or also constituting light responsive device |
| | 81 | With specific housing or contact structure |
| | 83 | Light coupled transistor structure |
| | 84 | Combined in integrated structure |
| | 86 | Active layer of indirect band gap semiconductor |
| | 87 | With means to facilitate electron-hole recombination (e.g., isoelectronic traps such as nitrogen in GaP) |
| | 88 | Plural light emitting devices (e.g., matrix, 7-segment array) |
| | 89 | Multi-color emission |
| | 91 | With shaped contacts or opaque masking |
| | 92 | Alphanumeric segmented array |
| | 93 | With electrical isolation means in integrated circuit structure |
| | 94 | With heterojunction |
| | 95 | With contoured external surface (e.g., dome shape to facilitate light emission) |
| | 96 | Plural heterojunctions in same device |
| | 99 | With housing or contact structure |
| | 100 | Encapsulated |
| | 101 | With particular dopant concentration or concentration profile (e.g., graded junction) |
| | 102 | With particular dopant material (e.g., zinc as dopant in GaAs) |
| | 103 | With particular semiconductor material |
| | 104 | TUNNELING PN JUNCTION (E.G., ESAKI DIODE) DEVICE |
| | 105 | In three or more terminal device |
| | 106 | Reverse bias tunneling structure (e.g., "backward" diode, true Zener diode) |
| | 107 | REGENERATIVE TYPE SWITCHING DEVICE (E.G., SCR, COMFET, THYRISTOR) |
| | 108 | Controlled by nonelectrical, nonoptical external signal (e.g., magnetic field, pressure, thermal) |
| | 109 | Having only two terminals and no control electrode (gate), e.g., Shockley diode |
| | 110 | More than four semiconductor layers of alternating conductivity types (e.g., pnpnpn structure, 5 layer bidirectional diacs, etc.) |
| | 111 | Triggered by V BO overvoltage means |
| | 112 | With highly-doped breakdown diode trigger |
| | 113 | With light activation |
| | 114 | With separate light detector integrated on chip with regenerative switching device |
| | 115 | With electrical trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.) |
| | 116 | With light conductor means (e.g., light fiber or light pipe) integral with device or device enclosure or package |
| | 118 | With groove or thinned light sensitive portion |
| | 119 | Bidirectional rectifier with control electrode (gate) (e.g., Triac) |
| | 120 | Six or more semiconductor layers of alternating conductivity types (e.g., npnpnpn structure) |
| | 121 | With diode or transistor in reverse path |
| | 122 | Lateral |
| | 123 | With trigger signal amplification (e.g., amplified gate) |
| | 124 | Combined with field effect transistor structure |
| | 126 | With means to separate a device into sections having different conductive polarity |
| | 128 | Having overlapping sections of different conductive polarity |
| | 129 | With means to increase reverse breakdown voltage |
| | 130 | Switching speed enhancement means |
| | 132 | Five or more layer unidirectional structure |
| | 133 | Combined with field effect transistor |
| | 134 | J-FET (junction field effect transistor) |
| | 137 | Having controllable emitter shunt |
| | 139 | With extended latchup current level (e.g., COMFET device) |
| | 140 | Combined with other solid-state active device in integrated structure |
| | 141 | Lateral structure, i.e., current flow parallel to main device surface |
| | 142 | Having impurity doping for gain reduction |
| | 143 | Having anode shunt means |
| | 144 | Cathode emitter or cathode electrode feature |
| | 145 | Low impedance channel contact extends below surface |
| | 146 | Combined with other solid-state active device in integrated structure |
| | 147 | With extended latchup current level (e.g., gate turn off "GTO" device) |
| | 148 | Having impurity doping for gain reduction |
| | 149 | Having anode shunt means |
| | 150 | With specified housing or external terminal |
| | 152 | Cathode emitter or cathode electrode feature |
| | 153 | Gate region or electrode feature |
| | 154 | With resistive region connecting separate sections of device |
| | 155 | With switching speed enhancement means (e.g., Schottky contact) |
| | 157 | With integrated trigger signal amplification means (e.g., amplified gate, "pilot thyristor", etc.) |
| | 158 | Three or more amplification stages |
| | 159 | Transistor as amplifier |
| | 160 | With distributed amplified current |
| | 161 | With a turn-off diode |
| | 162 | Lateral structure |
| | 163 | Emitter region feature |
| | 167 | Having at least four external electrodes |
| | 168 | With means to increase breakdown voltage |
| | 172 | With means to lower "ON" voltage drop |
| | 173 | Device protection (e.g., from overvoltage) |
| | 175 | With means to control triggering (e.g., gate electrode configuration, Zener diode firing, dV/Dt control, transient control by ferrite bead, etc.) |
| | 177 | With housing or external electrode |
| | 178 | With means to avoid stress between electrode and active device (e.g., thermal expansion matching of electrode to semiconductor) |
| | 180 | Stud mount |
| | 181 | With large area flexible electrodes in press contact with opposite sides of active semiconductor chip and surrounded by an insulating element, (e.g., ring) |
| | 183 | HETEROJUNCTION DEVICE |
| | 183.1 | Charge transfer device |
| | 184 | Light responsive structure |
| | 185 | Staircase (including graded composition) device |
| | 186 | Avalanche photodetection structure |
| | 187 | Having transistor structure |
| | 188 | Having narrow energy band gap (<<1eV) layer (e.g., PbSnTe, HgCdTe, etc.) |
| | 190 | With lattice constant mismatch (e.g., with buffer layer to accommodate mismatch) |
| | 191 | Having graded composition |
| | 192 | Field effect transistor |
| | 194 | Doping on side of heterojunction with lower carrier affinity (e.g., high electron mobility transistor (HEMT)) |
| | 196 | Both semiconductors of the heterojunction are the same conductivity type (i.e., either n or p) |
| | 197 | Bipolar transistor |
| | 199 | Avalanche diode (e.g., so-called "Zener" diode having breakdown voltage greater than 6 volts, including heterojunction IMPATT type microwave diodes) |
| | 201 | Between different group IV-VI or II-VI or III-V compounds other than GaAs/GaAlAs |
| | 202 | GATE ARRAYS |
| | 203 | With particular chip input/output means |
| | 204 | Having specific type of active device (e.g., CMOS) |
| | 205 | With bipolar transistors or with FETs of only one channel conductivity type (e.g., enhancement-depletion FETs) |
| | 206 | Particular layout of complementary FETs with regard to each other |
| | 207 | With particular power supply distribution means |
| | 208 | With particular signal path connections |
| | 212 | CONDUCTIVITY MODULATION DEVICE (E.G., UNIJUNCTION TRANSISTOR, DOUBLE-BASE DIODE, CONDUCTIVITY-MODULATED TRANSISTOR) |
| | 213 | FIELD EFFECT DEVICE |
| | 214 | Charge injection device |
| | 215 | Charge transfer device |
| | 216 | Majority signal carrier (e.g., buried or bulk channel, or peristaltic) |
| | 217 | Having a conductive means in direct contact with channel (e.g., non-insulated gate) |
| | 219 | Impurity concentration variation |
| | 220 | Vertically within channel (e.g., profiled) |
| | 221 | Along the length of the channel (e.g., doping variations for transfer directionality) |
| | 222 | Responsive to non-electrical external signal (e.g., imager) |
| | 224 | Channel confinement |
| | 225 | Non-electrical input responsive (e.g., light responsive imager, input programmed by size of storage sites for use as a read-only memory, etc.) |
| | 226 | Sensor element and charge transfer device are of different materials or on different substrates (e.g., "hybrid") |
| | 227 | With specified dopant (e.g., photoionizable, "extrinsic" detectors for infrared) |
| | 228 | Light responsive, back illuminated |
| | 229 | Having structure to improve output signal (e.g., exposure control structure) |
| | 231 | 2-dimensional area architecture |
| | 232 | Having alternating strips of sensor structures and register structures (e.g., interline imager) |
| | 233 | Sensors not overlaid by electrode (e.g., photodiodes) |
| | 234 | Single strip of sensors (e.g., linear imager) |
| | 235 | Electrical input |
| | 236 | Signal applied to field effect electrode |
| | 238 | Input signal responsive to signal charge in charge transfer device (e.g., regeneration or feedback) |
| | 239 | Signal charge detection type (e.g., floating diffusion or floating gate non-destructive output) |
| | 240 | Changing width or direction of channel (e.g., meandering channel) |
| | 241 | Multiple channels (e.g., converging or diverging or parallel channels) |
| | 242 | Vertical charge transfer |
| | 243 | Channel confinement |
| | 244 | Comprising a groove |
| | 245 | Structure for applying electric field into device (e.g., resistive electrode, acoustic traveling wave in channel) |
| | 246 | Phase structure (e.g., doping variations to provide asymmetry for 2-phase operation; more than four phases or "electrode per bit") |
| | 249 | Electrode structures or materials |
| | 251 | Substantially incomplete signal charge transfer (e.g., bucket brigade) |
| | 252 | Responsive to non-optical, non-electrical signal |
| | 253 | Chemical (e.g., ISFET, CHEMFET) |
| | 254 | Physical deformation (e.g., strain sensor, acoustic wave detector) |
| | 255 | With current flow along specified crystal axis (e.g., axis of maximum carrier mobility) |
| | 256 | Junction field effect transistor (unipolar transistor) |
| | 257 | Light responsive or combined with light responsive device |
| | 259 | Elongated active region acts as transmission line or distributed active element (e.g., "transmission line" field effect transistor) |
| | 260 | Same channel controlled by both junction and insulated gate electrodes, or by both Schottky barrier and pn junction gates (e.g., "taper isolated" memory cell) |
| | 261 | Junction gate region free of direct electrical connection (e.g., floating junction gate memory cell structure) |
| | 262 | Combined with insulated gate field effect transistor (IGFET) |
| | 263 | Vertical controlled current path |
| | 264 | Enhancement mode or with high resistivity channel (e.g., doping of 10 15 cm -3 or less) |
| | 265 | In integrated circuit |
| | 266 | With multiple parallel current paths (e.g., grid gate) |
| | 268 | Enhancement mode |
| | 270 | Plural, separately connected, gates control same channel region |
| | 271 | Load element or constant current source (e.g., with source to gate connection) |
| | 272 | Junction field effect transistor in integrated circuit |
| | 273 | With bipolar device |
| | 274 | Complementary junction field effect transistors |
| | 275 | Microwave integrated circuit (e.g., microstrip type) |
| | 276 | With contact or heat sink extending through hole in semiconductor substrate, or with electrode suspended over substrate (e.g., air bridge) |
| | 277 | With capacitive or inductive elements |
| | 278 | With devices vertically spaced in different layers of semiconductor material (e.g., "3-dimensional" integrated circuit) |
| | 279 | Pn junction gate in compound semiconductor material (e.g., GaAs) |
| | 280 | With Schottky gate |
| | 281 | Schottky gate to silicon semiconductor |
| | 282 | Gate closely aligned to source region |
| | 284 | Schottky gate in groove |
| | 285 | With profiled channel dopant concentration or profiled gate region dopant concentration (e.g., maximum dopant concentration below surface) |
| | 286 | With non-uniform channel thickness or width |
| | 287 | With multiple channels or channel segments connected in parallel, or with channel much wider than length between source and drain (e.g., power JFET) |
| | 288 | Having insulated electrode (e.g., MOSFET, MOS diode) |
| | 289 | Significant semiconductor chemical compound in bulk crystal (e.g., GaAs) |
| | 290 | Light responsive or combined with light responsive device |
| | 295 | With ferroelectric material layer |
| | 296 | Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell) |
| | 297 | With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection) |
| | 298 | Capacitor for signal storage in combination with non-volatile storage means |
| | 299 | Structure configured for voltage converter (e.g., charge pump, substrate bias generator) |
| | 300 | Capacitor coupled to, or forms gate of, insulated gate field effect transistor (e.g., non-destructive readout dynamic memory cell structure) |
| | 301 | Capacitor in trench |
| | 302 | Vertical transistor |
| | 303 | Stacked capacitor |
| | 304 | Storage node isolated by dielectric from semiconductor substrate |
| | 305 | With means to insulate adjacent storage nodes (e.g., channel stops or field oxide) |
| | 306 | Stacked capacitor |
| | 307 | Parallel interleaved capacitor electrode pairs (e.g., interdigitized) |
| | 308 |  With capacitor electrodes connection portion located centrally thereof (e.g., fin electrodes with central post) |
| | 309 | With increased effective electrode surface area (e.g., tortuous path, corrugated, or textured electrodes) |
| | 310 | With high dielectric constant insulator (e.g., Ta 2 O 5 ) |
| | 311 | Storage Node isolated by dielectric from semiconductor substrate |
| | 312 | Voltage variable capacitor (i. e., capacitance varies with applied voltage) |
| | 313 | Inversion layer capacitor |
| | 314 | Variable threshold (e.g., floating gate memory device) |
| | 315 | With floating gate electrode |
| | 316 | With additional contacted control electrode |
| | 317 | With irregularities on electrode to facilitate charging or discharging of floating electrode |
| | 318 | Additional control electrode is doped region in semiconductor substrate |
| | 319 | Plural additional contacted control electrodes |
| | 321 | With thin insulator region for charging or discharging floating electrode by quantum mechanical tunneling |
| | 322 | With charging or discharging by control voltage applied to source or drain region (e.g., by avalanche breakdown of drain junction) |
| | 323 | With means to facilitate light erasure |
| | 324 | Multiple insulator layers (e.g., MNOS structure) |
| | 327 | Short channel insulated gate field effect transistor |
| | 328 | Vertical channel or double diffused insulated gate field effect device provided with means to protect against excess voltage (e.g., gate protection diode) |
| | 329 | Gate controls vertical charge flow portion of channel (e.g., VMOS device) |
| | 335 | Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor) |
| | 336 | With lightly doped portion of drain region adjacent channel (e.g., LDD structure) |
| | 337 | In integrated circuit structure |
| | 339 | With means to increase breakdown voltage |
| | 340 | With means (other than self-alignment of the gate electrode) to decrease gate capacitance (e.g., shield electrode) |
| | 341 | Plural sections connected in parallel (e.g., power MOSFET) |
| | 343 | All contacts on same surface (e.g., lateral structure) |
| | 344 | With lightly doped portion of drain region adjacent channel (e.g., LDD structure) |
| | 345 | With means to prevent sub-surface currents, or with non-uniform channel doping |
| | 346 | Gate electrode overlaps the source or drain by no more than depth of source or drain (e.g., self-aligned gate) |
| | 347 | Single crystal semiconductor layer on insulating substrate (SOI) |
| | 348 | Depletion mode field effect transistor |
| | 349 | With means (e.g., a buried channel stop layer) to prevent leakage current along the interface of the semiconductor layer and the insulating substrate |
| | 350 | Insulated electrode device is combined with diverse type device (e.g., complementary MOSFETs, FET with resistor, etc.) |
| | 351 | Complementary field effect transistor structures only (i.e., not including bipolar transistors, resistors, or other components) |
| | 352 | Substrate is single crystal insulator (e.g., sapphire or spinel) |
| | 355 | With overvoltage protective means |
| | 356 | For protecting against gate insulator breakdown |
| | 364 | With resistive gate electrode |
| | 365 | With plural, separately connected, gate electrodes in same device |
| | 367 | Insulated gate controlled breakdown of pn junction (e.g., field plate diode) |
| | 368 | Insulated gate field effect transistor in integrated circuit |
| | 369 | Complementary insulated gate field effect transistors |
| | 370 | Combined with bipolar transistor |
| | 371 | Complementary transistors in wells of opposite conductivity types more heavily doped than the substrate region in which they are formed, e.g., twin wells |
| | 372 | With means to prevent latchup or parasitic conduction channels |
| | 373 | With pn junction to collect injected minority carriers to prevent parasitic bipolar transistor action |
| | 374 | Dielectric isolation means (e.g., dielectric layer in vertical grooves) |
| | 375 | With means to reduce substrate spreading resistance (e.g., heavily doped substrate) |
| | 377 | With polysilicon interconnections to source or drain regions (e.g., polysilicon laminated with silicide) |
| | 378 | Combined with bipolar transistor |
| | 379 | Combined with passive components (e.g., resistors) |
| | 382 | With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide) |
| | 383 | Contact of refractory or platinum group metal (e.g., molybdenum, tungsten, or titanium) |
| | 384 | Including silicide |
| | 385 | Multiple polysilicon layers |
| | 386 | With means to reduce parasitic capacitance |
| | 387 | Gate electrode overlaps at least one of source or drain by no more than depth of source or drain (e.g., self-aligned gate) |
| | 389 | With thick insulator over source or drain region |
| | 390 | Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM)) |
| | 391 | Selected groups of complete field effect devices having different threshold voltages (e.g., different channel dopant concentrations) |
| | 392 | Insulated gate field effect transistors of different threshold voltages in same integrated circuit (e.g., enhancement and depletion mode) |
| | 393 | Insulated gate field effect transistor adapted to function as load element for switching insulated gate field effect transistor |
| | 394 | With means to prevent parasitic conduction channels |
| | 395 | Thick insulator portion |
| | 400 | With heavily doped channel stop portion |
| | 401 | With specified physical layout (e.g., ring gate, source/drain regions shared between plural FETs, plural sections connected in parallel to form power MOSFET) |
| | 402 | With permanent threshold adjustment (e.g., depletion mode) |
| | 403 | With channel conductivity dopant same type as that of source and drain |
| | 405 | With gate insulator containing specified permanent charge |
| | 407 | With gate electrode of controlled workfunction material (e.g., low workfunction gate material) |
| | 408 | Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device) |
| | 409 | With means to increase breakdown voltage (e.g., field shield electrode, guard ring, etc.) |
| | 410 | Gate insulator includes material (including air or vacuum) other than SiO 2 |
| | 412 | Gate electrode of refractory material (e.g., polysilicon or a silicide of a refractory or platinum group metal) |
| | 414 | RESPONSIVE TO NON-ELECTRICAL SIGNAL (E.G., CHEMICAL, STRESS, LIGHT, OR MAGNETIC FIELD SENSORS) |
| | 415 | Physical deformation |
| | 416 | Acoustic wave |
| | 417 | Strain sensors |
| | 420 | Means to reduce sensitivity to physical deformation |
| | 421 | Magnetic field |
| | 422 | With magnetic field directing means (e.g., shield, pole piece, etc.) |
| | 423 | Bipolar transistor magnetic field sensor (e.g., lateral bipolar transistor) |
| | 424 | Sensor with region of high carrier recombination (e.g., magnetodiode with carriers deflected to recombination region by magnetic field) |
| | 425 | Magnetic field detector using compound semiconductor material (e.g., GaAs, InSb, etc.) |
| | 426 | Differential output (e.g., with offset adjustment means or with means to reduce temperature sensitivity) |
| | 427 | Magnetic field sensor in integrated circuit (e.g., in bipolar transistor integrated circuit) |
| | 428 | Electromagnetic or particle radiation |
| | 429 | Charged or elementary particles |
| | 431 | Light |
| | 432 | With optical element |
| | 433 | With housing or encapsulation |
| | 435 | With optical shield or mask means |
| | 436 | With means for increasing light absorption (e.g., redirection of unabsorbed light) |
| | 438 | Avalanche junction |
| | 439 | Containing dopant adapted for photoionization |
| | 440 | With different sensor portions responsive to different wavelengths (e.g., color imager) |
| | 441 | Narrow band gap semiconductor (<<1eV) (e.g., PbSnTe) |
| | 443 | Matrix or array (e.g., single line arrays) |
| | 444 | Light sensor elements overlie active switching elements in integrated circuit (e.g., where the sensor elements are deposited on an integrated circuit) |
| | 445 | With antiblooming means |
| | 446 | With specific isolation means in integrated circuit |
| | 447 | With backside illumination (e.g., having a thinned central area or a non-absorbing substrate) |
| | 448 | With particular electrode configuration |
| | 449 | Schottky barrier (e.g., a transparent Schottky metallic layer or a Schottky barrier containing at least one of indium or tin (e.g., SnO 2 , indium tin oxide)) |
| | 450 | With doping profile to adjust barrier height |
| | 451 | Responsive to light having lower energy (i.e., longer wavelength) than forbidden band gap energy of semiconductor (e.g., by excitation of carriers from metal into semiconductor) |
| | 452 | With edge protection, e.g., doped guard ring or mesa structure |
| | 453 | With specified Schottky metallic layer |
| | 457 | With particular contact geometry (e.g., ring or grid) |
| | 458 | PIN detector, including combinations with non-light responsive active devices |
| | 459 | With particular contact geometry (e.g., ring or grid, or bonding pad arrangement) |
| | 460 | With backside illumination (e.g., with a thinned central area or non-absorbing substrate) |
| | 461 | Light responsive pn junction |
| | 462 | Phototransistor |
| | 463 | With particular doping concentration |
| | 464 | With particular layer thickness (e.g., layer less than light absorption depth) |
| | 465 | Geometric configuration of junction (e.g., fingers) |
| | 466 | External physical configuration of semiconductor (e.g., mesas, grooves) |
| | 467 | Temperature |
| | 471 | SCHOTTKY BARRIER |
| | 472 | To compound semiconductor |
| | 474 | As active junction in bipolar transistor (e.g., Schottky collector) |
| | 475 | With doping profile to adjust barrier height |
| | 476 | In integrated structure |
| | 480 | In voltage variable capacitance diode |
| | 481 | Avalanche diode (e.g., so-called "Zener" diode having breakdown voltage greater than 6 volts) |
| | 483 | With means to prevent edge breakdown |
| | 485 | Specified materials |
| | 487 | WITH MEANS TO INCREASE BREAKDOWN VOLTAGE THRESHOLD |
| | 488 | Field relief electrode |
| | 491 | In integrated circuit |
| | 492 | With electric field controlling semiconductor layer having a low enough doping level in relationship to its thickness to be fully depleted prior to avalanche breakdown (e.g., RESURF devices) |
| | 493 | With electric field controlling semiconductor layer having a low enough doping level in relationship to its thickness to be fully depleted prior to avalanche breakdown (e.g., RESURF devices) |
| | 494 | Reverse-biased pn junction guard region |
| | 495 | Floating pn junction guard region |
| | 496 | With physical configuration of semiconductor surface to reduce electric field (e.g., reverse bevels, double bevels, stepped mesas, etc.) |
| | 497 | PUNCHTHROUGH STRUCTURE DEVICE (E.G., PUNCHTHROUGH TRANSISTOR, CAMEL BARRIER DIODE) |
| | 498 | Punchthrough region fully depleted at zero external applied bias voltage (e.g., camel barrier or planar doped barrier devices, or so-called "Bipolar SIT" devices) |
| | 499 | INTEGRATED CIRCUIT STRUCTURE WITH ELECTRICALLY ISOLATED COMPONENTS |
| | 500 | Including high voltage or high power devices isolated from low voltage or low power devices in the same integrated circuit |
| | 501 | Including dielectric isolation means |
| | 502 | High power or high voltage device extends completely through semiconductor substrate (e.g., backside collector contact) |
| | 503 | With contact or metallization configuration to reduce parasitic coupling (e.g., separate ground pads for different parts of integrated circuit) |
| | 504 | Including means for establishing a depletion region throughout a semiconductor layer for isolating devices in different portions of the layer (e.g., "JFET" isolation) |
| | 505 | With polycrystalline semiconductor isolation region in direct contact with single crystal active semiconductor material |
| | 506 | Including dielectric isolation means |
| | 507 | With single crystal insulating substrate (e.g., sapphire) |
| | 508 | With metallic conductor within isolating dielectric or between semiconductor and isolating dielectric (e.g., metal shield layer or internal connection layer) |
| | 509 | Combined with pn junction isolation (e.g., isoplanar, LOCOS) |
| | 510 | Dielectric in groove |
| | 511 | With complementary (npn and pnp) bipolar transistor structures |
| | 513 | Vertical walled groove |
| | 515 | With active junction abutting groove (e.g., "walled emitter") |
| | 516 | With passive component (e.g., resistor, capacitor, etc.) |
| | 517 | With bipolar transistor structure |
| | 519 | Including heavily doped channel stop region adjacent groove |
| | 520 | Conductive filling in dielectric-lined groove (e.g., polysilicon backfill) |
| | 521 | Sides of grooves along major crystal planes (e.g., (111), (100) planes, etc.) |
| | 522 | Air isolation (e.g., beam lead supported semiconductor islands) |
| | 523 | Isolation by region of intrinsic (undoped) semiconductor material (e.g., including region physically damaged by proton bombardment) |
| | 524 | Full dielectric isolation with polycrystalline semiconductor substrate |
| | 526 | With bipolar transistor structure |
| | 528 | Passive components in ICs |
| | 529 | Including programmable passive component (e.g., fuse) |
| | 531 | Including inductive element |
| | 532 | Including capacitor component |
| | 533 | Combined with resistor to form RC filter structure |
| | 534 | With means to increase surface area (e.g., grooves, ridges, etc.) |
| | 535 | Both terminals of capacitor isolated from substrate |
| | 536 | Including resistive element |
| | 544 | With pn junction isolation |
| | 545 | With means to control isolation junction capacitance (e.g., lightly doped layer at isolation junction to increase depletion layer width) |
| | 546 | With structural means to protect against excess or reversed polarity voltage |
| | 547 | With structural means to control parasitic transistor action or leakage current |
| | 548 | At least three regions of alternating conductivity types with dopant concentration gradients decreasing from surface of semiconductor (e.g., "triple-diffused" integrated circuit) |
| | 551 | Including voltage reference element (e.g., avalanche diode, so-called "Zener diode" with breakdown voltage greater than 6 volts or with positive temperature coefficient of breakdown voltage) |
| | 552 | With bipolar transistor structure |
| | 553 | Transistors of same conductivity type (e.g., npn) having different current gain or different operating voltage characteristics |
| | 554 | With connecting region made of polycrystalline semiconductor material (e.g., polysilicon base contact) |
| | 555 | Complementary bipolar transistor structures (e.g., integrated injection logic, I 2 L) |
| | 557 | Lateral bipolar transistor structure |
| | 558 | With base region doping concentration step or gradient or with means to increase current gain |
| | 559 | With active region formed along groove or exposed edge in semiconductor |
| | 560 | With multiple collectors or emitters |
| | 563 | With multiple separately connected emitter, collector, or base regions in same transistor structure |
| | 565 | BIPOLAR TRANSISTOR STRUCTURE |
| | 566 | Plural non-isolated transistor structures in same structure |
| | 567 | Darlington configuration (i.e., emitter to collector current of input transistor supplied to base region of output transistor) |
| | 568 | More than two Darlington-connected transistors |
| | 569 | Complementary Darlington-connected transistors |
| | 570 | With active components in addition to Darlington transistors (e.g., antisaturation diode, bleeder diode connected antiparallel to input transistor base-emitter junction, etc.) |
| | 571 | Non-planar structure (e.g., mesa emitter, or having a groove to define resistor) |
| | 572 | With resistance means connected between transistor base regions |
| | 573 | With housing or contact structure or configuration |
| | 574 | Complementary transistors share common active region (e.g., integrated injection logic, I 2 L) |
| | 577 | Including additional component in same, non-isolated structure (e.g., transistor with diode, transistor with resistor, etc.) |
| | 578 | With enlarged emitter area (e.g., power device) |
| | 579 | With separate emitter areas connected in parallel |
| | 580 | With current ballasting means (e.g., emitter ballasting resistors or base current ballasting means) |
| | 582 | With current ballasting means (e.g., emitter ballasting resistors or base current ballasting resistors) |
| | 583 | With means to reduce transistor action in selected portions of transistor (e.g., heavy base region doping under central web of emitter to prevent secondary breakdown) |
| | 584 | With housing or contact (i.e., electrode) means |
| | 585 | With means to increase inverse gain |
| | 586 | With non-planar semiconductor surface (e.g., groove, mesa, bevel, etc.) |
| | 587 | With specified electrode means |
| | 589 | Avalanche transistor |
| | 590 | With means to reduce minority carrier lifetime (e.g., region of deep level dopant or region of crystal damage) |
| | 591 | With emitter region having specified doping concentration profile (e.g., high-low concentration step) |
| | 593 | With means to increase current gain or operating frequency |
| | 594 | WITH GROOVE TO DEFINE PLURAL DIODES |
| | 595 | VOLTAGE VARIABLE CAPACITANCE DEVICE |
| | 596 | With specified dopant profile |
| | 597 | Retrograde dopant profile (e.g., dopant concentration decreases with distance from rectifying junction) |
| | 598 | With plural junctions whose depletion regions merge to vary voltage dependence |
| | 599 | With means to increase active junction area (e.g., grooved or convoluted surface) |
| | 600 | With physical configuration to vary voltage dependence (e.g., mesa) |
| | 601 | Plural diodes in same non-isolated structure, or device having three or more terminals |
| | 602 | With specified housing or contact |
| | 603 | AVALANCHE DIODE (E.G., SO-CALLED "ZENER" DIODE HAVING BREAKDOWN VOLTAGE GREATER THAN 6 VOLTS) |
| | 604 | Microwave transit time device (e.g., IMPATT diode) |
| | 605 | With means to limit area of breakdown (e.g., guard ring having higher breakdown voltage) |
| | 607 | WITH SPECIFIED DOPANT (E.G., PLURAL DOPANTS OF SAME CONDUCTIVITY IN SAME REGION) |
| | 608 | Switching device based on filling and emptying of deep energy levels |
| | 609 | For compound semiconductor (e.g., deep level dopant) |
| | 610 | Deep level dopant |
| | 613 | INCLUDING SEMICONDUCTOR MATERIAL OTHER THAN SILICON OR GALLIUM ARSENIDE (GAAS) (E.G., PB X SN 1-X TE) |
| | 614 | Group II-VI compound (e.g., CdTe, Hg x Cd 1-x Te) |
| | 615 | Group III-V compound (e.g., InP) |
| | 616 | Containing germanium, Ge |
| | 617 | INCLUDING REGION CONTAINING CRYSTAL DAMAGE |
| | 618 | PHYSICAL CONFIGURATION OF SEMICONDUCTOR (E.G., MESA, BEVEL, GROOVE, ETC.) |
| | 619 | With thin active central semiconductor portion surrounded by thicker inactive shoulder (e.g., for mechanical support) |
| | 621 | With electrical contact in hole in semiconductor (e.g., lead extends through semiconductor body) |
| | 622 | Groove |
| | 623 | Mesa structure (e.g., including undercut or stepped mesa configuration or having constant slope taper) |
| | 624 | With low resistance ohmic connection means along exposed mesa edge (e.g., contact or heavily doped region along exposed mesa to reduce "skin effect" losses in microwave diode) |
| | 626 | Combined with passivating coating |
| | 627 | With specified crystal plane or axis |
| | 629 | WITH MEANS TO CONTROL SURFACE EFFECTS |
| | 630 | With inversion-preventing shield electrode |
| | 631 | In compound semiconductor material (e.g., GaAs) |
| | 632 | Insulating coating |
| | 633 | With thermal expansion compensation (e.g., thermal expansion of glass passivant matched to that of semiconductor) |
| | 634 | Insulating coating of glass composition containing component to adjust melting or softening temperature (e.g., low melting point glass) |
| | 635 | Multiple layers |
| | 636 | At least one layer of semi-insulating material |
| | 637 | Three or more insulating layers |
| | 638 | With discontinuous or varying thickness layer (e.g., layer covers only selected portions of semiconductor) |
| | 639 | At least one layer of silicon oxynitride |
| | 640 | At least one layer of silicon nitride |
| | 642 | At least one layer of organic material |
| | 644 | At least one layer of glass |
| | 645 | Insulating layer containing specified electrical charge (e.g., net negative electrical charge) |
| | 646 | Coating of semi-insulating material (e.g., amorphous silicon or silicon-rich silicon oxide) |
| | 647 | Insulating layer recessed into semiconductor surface (e.g., LOCOS oxide) |
| | 649 | Insulating layer of silicon nitride or silicon oxynitride |
| | 650 | Insulating layer of glass |
| | 651 | Details of insulating layer electrical charge (e.g., negative insulator layer charge) |
| | 652 | Channel stop layer |
| | 653 | WITH SPECIFIED SHAPE OF PN JUNCTION |
| | 655 | WITH SPECIFIED IMPURITY CONCENTRATION GRADIENT |
| | 656 | With high resistivity (e.g., "intrinsic") layer between P and N layers (e.g., PIN diode) |
| | 657 | Stepped profile |
| | 658 | PLATE TYPE RECTIFIER ARRAY |
| | 659 | WITH SHIELDING (E.G., ELECTRICAL OR MAGNETIC SHIELDING, OR FROM ELECTROMAGNETIC RADIATION OR CHARGED PARTICLES) |
| | 660 | With means to shield device contained in housing or package from charged particles (e.g., alpha particles) or highly ionizing radiation (i.e., hard X-rays or shorter wavelength) |
| | 661 | SUPERCONDUCTIVE CONTACT OR LEAD |
| | 664 | TRANSMISSION LINE LEAD (E.G., STRIPLINE, COAX, ETC.) |
| | 665 | CONTACTS OR LEADS INCLUDING FUSIBLE LINK MEANS OR NOISE SUPPRESSION MEANS |
| | 666 | LEAD FRAME |
| | 667 | With dam or vent for encapsulant |
| | 668 | On insulating carrier other than a printed circuit board |
| | 669 | With stress relief |
| | 670 | With separate tie bar element or plural tie bars |
| | 672 | Small lead frame (e.g., "spider" frame) for connecting a large lead frame to a semiconductor chip |
| | 673 | With bumps on ends of lead fingers to connect to semiconductor |
| | 674 | With means for controlling lead tension |
| | 675 | With heat sink means |
| | 676 | With structure for mounting semiconductor chip to lead frame (e.g., configuration of die bonding flag, absence of a die bonding flag, recess for LED) |
| | 677 | Of specified material other than copper (e.g., Kovar (T.M.)) |
| | 678 | HOUSING OR PACKAGE |
| | 679 | Smart (e.g., credit) card package |
| | 680 | With window means |
| | 682 | With desiccant, getter, or gas filling |
| | 683 | With means to prevent explosion of package |
| | 684 | With semiconductor element forming part (e.g., base, of housing) |
| | 685 | Multiple housings |
| | 687 | Housing or package filled with solid or liquid electrically insulating material |
| | 688 | With large area flexible electrodes in press contact with opposite sides of active semiconductor chip and surrounded by an insulating element, e.g., ring |
| | 690 | With contact or lead |
| | 691 | Having power distribution means (e.g., bus structure) |
| | 692 | With particular lead geometry |
| | 698 | With specific electrical feedthrough structure |
| | 700 | Multiple contact layers separated from each other by insulator means and forming part of a package or housing (e.g., plural ceramic layer package) |
| | 701 | Insulating material |
| | 702 | Of insulating material other than ceramic |
| | 703 | Composite ceramic, or single ceramic with metal |
| | 704 | Cap or lid |
| | 705 | Of high thermal conductivity ceramic (e.g., BeO) |
| | 706 | With heat sink |
| | 708 | Entirely of metal except for feedthrough |
| | 709 | With specified insulator to isolate device from housing |
| | 710 | With specified means (e.g., lip) to seal base to cap |
| | 711 | With raised portion of base for mounting semiconductor chip |
| | 712 | With provision for cooling the housing or its contents |
| | 713 | For integrated circuit |
| | 714 | Liquid coolant |
| | 717 | Isolation of cooling means (e.g., heat sink) by an electrically insulating element (e.g., spacer) |
| | 718 | Heat dissipating element held in place by clamping or spring means |
| | 720 | Heat dissipating element has high thermal conductivity insert (e.g., copper slug in aluminum heat sink) |
| | 721 | With gas coolant |
| | 723 | For plural devices |
| | 727 | Device held in place by clamping |
| | 728 | For high frequency (e.g., microwave) device |
| | 729 | Portion of housing of specific materials |
| | 730 | Outside periphery of package having specified shape or configuration |
| | 731 | With housing mount |
| | 734 | COMBINED WITH ELECTRICAL CONTACT OR LEAD |
| | 735 | Beam leads (i.e., leads that extend beyond the ends or sides of a chip component) |
| | 737 | Bump leads |
| | 739 | With textured surface |
| | 740 | With means to prevent contact from penetrating shallow PN junction (e.g., prevention of aluminum "spiking") |
| | 741 | Of specified material other than unalloyed aluminum |
| | 742 | With a semiconductor conductivity substitution type dopant (e.g., germanium in the case of a gallium arsenide semiconductor) in a contact metal) |
| | 744 | For compound semiconductor material |
| | 746 | Composite material (e.g., fibers or strands embedded in solid matrix) |
| | 747 | With thermal expansion matching of contact or lead material to semiconductor active device |
| | 749 | At least portion of which is transparent to ultraviolet, visible or infrared light |
| | 750 | Layered |
| | 751 | At least one layer forms a diffusion barrier |
| | 752 | Planarized to top of insulating layer |
| | 753 | With adhesion promoting means (e.g., layer of material) to promote adhesion of contact to an insulating layer |
| | 754 | At least one layer of silicide or polycrystalline silicon |
| | 755 | Polysilicon laminated with silicide |
| | 756 | Multiple polysilicon layers |
| | 757 | Silicide of refractory or platinum group metal |
| | 758 | Multiple metal levels on semiconductor, separated by insulating layer (e.g., multiple level metallization for integrated circuit) |
| | 759 | Including organic insulating material between metal levels |
| | 760 | Separating insulating layer is laminate or composite of plural insulating materials (e.g., silicon oxide on silicon nitride, silicon oxynitride) |
| | 761 | At least one layer containing vanadium, hafnium, niobium, zirconium, or tantalum |
| | 762 | At least one layer containing silver or copper |
| | 763 | At least one layer of molybdenum, titanium, or tungsten |
| | 765 | At least one layer of an alloy containing aluminum |
| | 766 | At least one layer containing chromium or nickel |
| | 767 | Resistive to electromigration or diffusion of the contact or lead material |
| | 768 | Refractory or platinum group metal or alloy or silicide thereof |
| | 769 | Platinum group metal or silicide thereof |
| | 770 | Molybdenum, tungsten, or titanium or their silicides |
| | 771 | Alloy containing aluminum |
| | 772 | Solder composition |
| | 773 | Of specified configuration |
| | 774 | Via (interconnection hole) shape |
| | 775 | Varying width or thickness of conductor |
| | 776 | Cross-over arrangement, component or structure |
| | 777 | Chip mounted on chip |
| | 778 | Flip chip |
| | 779 | Solder wettable contact, lead, or bond |
| | 780 | Ball or nail head type contact, lead, or bond |
| | 782 | Die bond |
| | 784 | Wire contact, lead, or bond |
| | 785 | By pressure alone |
| | 786 | Configuration or pattern of bonds |
| | 787 | ENCAPSULATED |
| | 788 | With specified encapsulant |
| | 789 | With specified filler material |
| | 790 | Plural encapsulating layers |
| | 791 | Including polysiloxane (e.g., silicone resin) |
| | 792 | Including polyimide |
| | 793 | Including epoxide |
| | 794 | Including glass |
| | 795 | With specified filler material |
| | 796 | With heat sink embedded in encapsulant |
| | 797 | ALIGNMENT MARKS |
| | 798 | MISCELLANEOUS |
| E-SUBCLASSES | ||
| The following subclasses beginning with the letter E are E-subclasses. Each E-subclass corresponds in scope to a classification in a foreign classification system, for example, the European Classification system (ECLA). The foreign classification equivalent to an E-subclass is identified in the subclass definition. In addition to US documents classified in E-subclasses by US examiners, documents are regularly classified in E-subclasses according to the classification practices of any foreign Offices identified in parentheses at the end of the title. For example, "(EPO)" at the end of a title indicates both European and US patent documents, as classified by the EPO, are regularly added to the subclass. E-subclasses may contain subject matter outside the scope of this class.Consult their definitions, or the documents themselves to clarify or interpret titles. |
| | E47.001 | BULK NEGATIVE RESISTANCE EFFECT DEVICES, E.G., GUNN-EFFECT DEVICES, PROCESSES, OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT OF SUCH DEVICES, OR OF PARTS THEREOF (EPO) |
| | E47.002 | Gunn-effect devices or transferred electron devices (EPO) |
| | E47.005 | Processes or apparatus peculiar to manufacture or treatment of these devices or of parts thereof (EPO) |
| | E39.001 | DEVICES USING SUPERCONDUCTIVITY, PROCESSES, OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT OF SUCH DEVICES, OR OF PARTS THEREOF (EPO) |
| | E39.002 | Containers or mountings (EPO) |
| | E39.004 | Characterized by current path (EPO) |
| | E39.005 | Characterized by shape of element (EPO) |
| | E39.006 | Characterized by material (EPO) |
| | E39.007 | Organic materials (EPO) |
| | E39.008 | Fullerene superconductors, e.g., soccerball-shaped allotrope of carbon, e.g., C60, C94 (EPO) |
| | E39.009 | Ceramic materials (EPO) |
| | E39.012 | Devices comprising junction of dissimilar materials, e.g., Josephson-effect devices (EPO) |
| | E39.013 | Single electron tunnelling devices (EPO) |
| | E39.014 | Josephson-effect devices (EPO) |
| | E39.016 | Three or more electrode devices, e.g., transistor-like structures (EPO) |
| | E39.017 | Permanent superconductor devices (EPO) |
| | E51.001 | ORGANIC SOLID STATE DEVICES, PROCESSES OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT OF SUCH DEVICES OR OF PARTS THEREOF |
| | E51.002 | Structural detail of device (EPO) |
| | E51.003 | Organic solid-state device adapted for rectifying, amplifying, oscillating, or switching, or capacitors or resistors with potential or surface barrier (EPO) |
| | E51.004 | Controllable by only signal applied to control electrode (e.g., base of bipolar transistor, gate of field-effect transistor) (EPO) |
| | E51.012 | Radiation-sensitive organic solid-state device (EPO) |
| | E51.013 | Metal-organic semiconductor-metal device (EPO) |
| | E51.014 | Comprising bulk heterojunction (EPO) |
| | E51.015 | Comprising organic/inorganic heterojunction (EPO) |
| | E51.016 | Majority carrier device using sensitization of wide band gap semiconductor (e.g., TiO 2 ) (EPO) |
| | E51.017 | Comprising organic semiconductor-organic semiconductor heterojunction (EPO) |
| | E51.018 | Light-emitting organic solid-state device with potential or surface barrier (EPO) |
| | E51.019 | Electrode (EPO) |
| | E51.02 | Encapsulation (EPO) |
| | E51.021 | Arrangements for extracting light from device (e.g., Bragg reflector pair) (EPO) |
| | E51.022 | Multicolor organic light-emitting device (OLED) (EPO) |
| | E51.023 | Molecular electronic device (EPO) |
| | E51.024 | Selection of material for organic solid-state device (EPO) |
| | E51.025 | For organic solid-state device adapted for rectifying, amplifying, oscillating, or switching, or capacitors or resistors with potential or surface barrier (EPO) |
| | E51.026 | For radiation-sensitive or light-emitting organic solid-state device with potential or surface barrier (EPO) |
| | E51.027 | Organic polymer or oligomer (EPO) |
| | E51.028 | Comprising aromatic, heteroaromatic, or arrylic chains (e.g., polyaniline, polyphenylene, polyphenylene vinylene) (EPO) |
| | E51.029 | Heteroaromatic compound comprising sulfur or selene (e.g., polythiophene) (EPO) |
| | E51.031 | Polyphenylenevinylene and derivatives (EPO) |
| | E51.032 | Polyflurorene and derivative (EPO) |
| | E51.033 | Comprising aliphatic or olefinic chains (e.g., polyN-vinylcarbazol, PVC, PTFE) (EPO) |
| | E51.036 | Copolymers (EPO) |
| | E51.037 | Ladder-type polymer (EPO) |
| | E51.038 | Carbon-containing materials (EPO) |
| | E51.041 | Coordination compound (e.g., porphyrin, phthalocyanine, metal(II) polypyridine complexes) (EPO) |
| | E51.042 | Phthalocyanine (EPO) |
| | E51.043 | Metal complexes comprising Group IIIB metal (Al, Ga, In, or Ti) (e.g., Tris (8-hydroxyquinoline) aluminium (Alq3)) (EPO) |
| | E51.044 | Transition metal complexes (e.g., Ru(II) polypyridine complexes) (EPO) |
| | E51.045 | Biomolecule or macromolecule (e.g., proteins, ATP, chlorophyl, beta-carotene, lipids, enzymes) (EPO) |
| | E51.046 | Silicon-containing organic semiconductor (EPO) |
| | E51.047 | Macromolecular system with low molecular weight (e.g., cyanine dyes, coumarine dyes, tetrathiafulvalene) (EPO) |
| | E51.048 | Charge transfer complexes (EPO) |
| | E51.049 | Polycondensed aromatic or heteroaromatic compound (e.g., pyrene, perylene, pentacene) (EPO) |
| | E51.05 | Aromatic compound containing heteroatom (e.g., perylenetetracarboxylic dianhydride, perylene tetracarboxylic diimide) (EPO) |
| | E51.051 | Amine compound having at least two aryl on amine-nitrogen atom (e.g., triphenylamine) (EPO) |
| | E51.052 | Langmuir Blodgett film (EPO) |
| | E43.001 | SEMICONDUCTOR OR SOLID-STATE DEVICES USING GALVANO-MAGNETIC OR SIMILAR MAGNETIC EFFECTS, PROCESSES OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT OF SUCH DEVICES, OR OF PARTS THEREOF (EPO) |
| | E43.002 | Hall-effect devices (EPO) |
| | E43.004 | Magnetic-field-controlled resistors (EPO) |
| | E43.005 | Selection of materials (EPO) |
| | E43.006 | Processes or apparatus peculiar to manufacture or treatment of these devices or of parts thereof (EPO) |
| | E33.001 | LIGHT EMITTING SEMICONDUCTOR DEVICES HAVING A POTENTIAL OR A SURFACE BARRIER, PROCESSES OR APPARATUS PECULIAR TO THE MANUFACTURE OR TREATMENT OF SUCH DEVICES, OR OF PARTS THEREOF |
| | E33.002 | Device characterized by semiconductor body (EPO) |
| | E33.003 | Particular crystalline orientation or structure (EPO) |
| | E33.005 | Shape or structure (e.g., shape of epitaxial layer) (EPO) |
| | E33.006 | Shape of semiconductor body (EPO) |
| | E33.007 | Shape of potential barrier (EPO) |
| | E33.008 | Multiple quantum well structure (EPO) |
| | E33.009 | Including, apart from doping materials or other only impurities, Group IV element (e.g., Si-SiGe superlattice) (EPO) |
| | E33.01 | Doped superlattice (e.g., nipi superlattice) (EPO) |
| | E33.011 | For current confinement (EPO) |
| | E33.012 | Multiple active regions between two electrodes (e.g., stacks) (EPO) |
| | E33.013 | Material of active region (EPO) |
| | E33.014 | In different regions (EPO) |
| | E33.015 | Comprising only Group IV element (EPO) |
| | E33.016 | With heterojunction (EPO) |
| | E33.017 | Characterized by doping material (EPO) |
| | E33.018 | Including porous Si (EPO) |
| | E33.019 | Comprising only Group II-VI compound (EPO) |
| | E33.02 | Ternary or quaternary compound (e.g., CdHgTe) (EPO) |
| | E33.022 | Characterized by doping material (EPO) |
| | E33.023 | Comprising only Group III-V compound (EPO) |
| | E33.024 | Binary compound (e.g., GaAs) (EPO) |
| | E33.026 | Ternary or quaternary compound (e.g., AlGaAs) (EPO) |
| | E33.029 | Characterized by doping material (EPO) |
| | E33.031 | Including ternary or quaternary compound (e.g., AlGaAs) (EPO) |
| | E33.035 | Comprising only Group IV compound (e.g., SiC) (EPO) |
| | E33.037 | Comprising compound other than Group II-VI, III-V, and IV compound (EPO) |
| | E33.043 | Physical imperfections (e.g., particular concentration or distribution of impurity) (EPO) |
| | E33.044 | Device characterized by their operation (EPO) |
| | E33.045 | Having p-n or hi-lo junction (EPO) |
| | E33.048 | Having heterojunction or graded gap (EPO) |
| | E33.049 | Comprising only Group III-V compound (EPO) |
| | E33.05 | Comprising only Group II-IV compound (EPO) |
| | E33.051 | Having Schottky barrier (EPO) |
| | E33.052 | Having MIS barrier layer (EPO) |
| | E33.053 | Characterized by field-effect operation (EPO) |
| | E33.054 | Device being superluminescent diode (EPO) |
| | E33.055 | Detail of nonsemiconductor component other than light-emitting semiconductor device (EPO) |
| | E33.056 | Packaging (EPO) |
| | E33.06 | Coatings (EPO) |
| | E33.062 | Electrodes (EPO) |
| | E33.063 | Characterized by material (EPO) |
| | E33.064 | Comprising transparent conductive layers (e.g., transparent conductive oxides (TCO), indium tin oxide (ITO)) (EPO) |
| | E33.065 | Characterized by shape (EPO) |
| | E33.066 | Electrical contact or lead (e.g., lead frame) (EPO) |
| | E33.067 | Means for light extraction or guiding (EPO) |
| | E33.068 | Integrated with device (e.g., back surface reflector, lens) (EPO) |
| | E33.069 | Comprising resonant cavity structure (e.g., Bragg reflector pair) (EPO) |
| | E33.07 | Comprising window layer (EPO) |
| | E33.071 | Not integrated with device (EPO) |
| | E33.074 | Scattering means (e.g., surface roughening) (EPO) |
| | E33.075 | With means for cooling or heating (EPO) |
| | E33.076 | With means for light detecting (e.g., photodetector) (EPO) |
| | E33.077 | Monolithic integration with photosensitive device (EPO) |
| | E31.001 | SEMICONDUCTOR DEVICES RESPONSIVE OR SENSITIVE TO ELECTROMAGNETIC RADIATION (E.G., INFRARED RADIATION, ADAPTED FOR CONVERSION OF RADIATION INTO ELECTRICAL ENERGY OR FOR CONTROL OF ELECTRICAL ENERGY BY SUCH RADIATION PROCESSES, OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT OF SUCH DEVICES, OR OF PARTS THEREOF) (EPO) |
| | E31.002 | Characterized by semiconductor body (EPO) |
| | E31.003 | Characterized by semiconductor body material (EPO) |
| | E31.004 | Inorganic materials (EPO) |
| | E31.005 | In different semiconductor regions (e.g., Cu 2 X/CdX heterojunction and X being Group VI element) (EPO) |
| | E31.006 | Comprising only Cu 2 X/CdX heterojunction and X being Group VI element (EPO) |
| | E31.007 | Comprising only heterojunction including Group I-III-VI compound (e.g., CdS/CuInSe 2 heterojunction) (EPO) |
| | E31.008 | Selenium or tellurium (EPO) |
| | E31.009 | For device having potential or surface barrier (EPO) |
| | E31.01 | Characterized by doping material (EPO) |
| | E31.011 | Including, apart from doping material or other impurity, only Group IV element (EPO) |
| | E31.012 | For device having potential or surface barrier (EPO) |
| | E31.013 | Comprising porous silicon as part of active layer (EPO) |
| | E31.014 | Characterized by doping material (EPO) |
| | E31.015 | Including, apart from doping material or other impurity, only Group II-VI compound (e.g., CdS, ZnS, HgCdTe) (EPO) |
| | E31.016 | For device having potential or surface barrier (EPO) |
| | E31.018 | Including ternary compound (e.g., HgCdTe) (EPO) |
| | E31.019 | Including, apart from doping material or other impurity, only Group III-V compound (EPO) |
| | E31.02 | For device having potential or surface barrier (EPO) |
| | E31.022 | Including ternary or quaternary compound (EPO) |
| | E31.023 | Including, apart from doping material or other impurity, only Group IV compound (e.g., SiC) (EPO) |
| | E31.024 | For device having potential or surface barrier (EPO) |
| | E31.025 | Characterized by doping material (EPO) |
| | E31.026 | Including, apart from doping material or other impurity, only compound other than Group II-VI, III-V, and IV compound (EPO) |
| | E31.032 | Characterized by semiconductor body shape, relative size, or disposition of semiconductor regions (EPO) |
| | E31.033 | Multiple quantum well structure (EPO) |
| | E31.034 | Characterized by amorphous semiconductor layer (EPO) |
| | E31.035 | Including, apart from doping material or other impurity, only Group IV element or compound (e.g., Si-SiGe superlattice) (EPO) |
| | E31.036 | Doping superlattice (e.g., nipi superlattice) (EPO) |
| | E31.037 | For device having potential or surface barrier (EPO) |
| | E31.04 | Characterized by semiconductor body crystalline structure or plane (EPO) |
| | E31.041 | Including thin film deposited on metallic or insulating substrate (EPO) |
| | E31.043 | Including polycrystalline semiconductor (EPO) |
| | E31.047 | Including amorphous semiconductor (EPO) |
| | E31.051 | Including other nonmonocrystalline material (e.g., semiconductor particles embedded in insulating material) (EPO) |
| | E31.052 | Adapted to control current flow through device (e.g., photoresistor) (EPO) |
| | E31.053 | For device having potential or surface barrier (e.g., phototransistor) (EPO) |
| | E31.054 | Device sensitive to infrared, visible, or ultraviolet radiation (EPO) |
| | E31.055 | Characterized by only one potential or surface barrier (EPO) |
| | E31.056 | Potential barrier being of point contact type (EPO) |
| | E31.057 | PN homojunction potential barrier (EPO) |
| | E31.058 |  Device comprising active layer formed only by Group II-VI compound (e.g., HgCdTe IR photodiode) (EPO) |
| | E31.059 | Device comprising active layer formed only by Group III-V compound (EPO) |
| | E31.06 | Device comprising active layer formed only by Group IV compound (EPO) |
| | E31.061 | PIN potential barrier (EPO) |
| | E31.063 | Potential barrier working in avalanche mode (e.g., avalanche photodiode) (EPO) |
| | E31.065 | Schottky potential barrier (EPO) |
| | E31.067 | PN heterojunction potential barrier (EPO) |
| | E31.068 | Characterized by two potential or surface barriers (EPO) |
| | E31.07 | Characterized by at least three potential barriers (EPO) |
| | E31.073 | Field-effect type (e.g., junction field-effect phototransistor) (EPO) |
| | E31.086 | Device sensitive to very short wavelength (e.g., X-ray, gamma-ray, or corpuscular radiation) (EPO) |
| | E31.092 | Device being sensitive to very short wavelength (e.g., X-ray, gamma-ray) (EPO) |
| | E31.093 | Device sensitive to infrared, visible, or ultraviolet radiation (EPO) |
| | E31.095 | Structurally associated with electric light source (e.g., electroluminescent light source) (EPO) |
| | E31.096 | Hybrid device containing photosensitive and electroluminescent components within one single body (EPO) |
| | E31.097 | Light source controlled by radiation-sensitive semiconductor device (e.g., image converter, image amplifier, image storage device) (EPO) |
| | E31.098 | Device without potential or surface barrier (EPO) |
| | E31.099 | Light source being semiconductor device with potential or surface barrier (e.g., light-emitting diode) (EPO) |
| | E31.1 | Device with potential or surface barrier (EPO) |
| | E31.101 | Semiconductor light source and radiation-sensitive semiconductor device both having potential or surface barrier (EPO) |
| | E31.103 | Radiation-sensitive semiconductor device controlled by light source (EPO) |
| | E31.104 | Radiation-sensitive semiconductor device without potential or surface barrier (e.g., photoresistor) (EPO) |
| | E31.105 | Light source being semiconductor device having potential or surface barrier (e.g., light-emitting diode) (EPO) |
| | E31.106 | Optical potentiometer (EPO) |
| | E31.107 | Radiation-sensitive semiconductor device with potential or surface barrier (EPO) |
| | E31.108 | Semiconductor light source and radiation-sensitive semiconductor device both having potential or surface barrier (EPO) |
| | E31.11 | Detail of nonsemiconductor component of radiation-sensitive semiconductor device (EPO) |
| | E31.111 | Input/output circuit of device (EPO) |
| | E31.113 | Circuit arrangement of general character for device (EPO) |
| | E31.117 | Encapsulation (EPO) |
| | E31.119 | Coatings (EPO) |
| | E31.124 | Electrode (EPO) |
| | E31.125 | For device having potential or surface barrier (EPO) |
| | E31.126 | Transparent conductive layer (e.g., transparent conductive oxide (TCO), indium tin oxide (ITO) layer) (EPO) |
| | E31.127 | Optical element associated with device (EPO) |
| | E31.128 | Device having potential or surface barrier (EPO) |
| | E31.129 | Comprising luminescent member (e.g., fluorescent sheet) (EPO) |
| | E31.13 | Texturized surface (EPO) |
| | E31.131 | Arrangement for temperature regulation (e.g., cooling, heating, or ventilating) (EPO) |
| | E27.001 | DEVICE CONSISTING OF A PLURALITY OF SEMICONDUCTOR OR OTHER SOLID STATE COMPONENTS FORMED IN OR ON A COMMON SUBSTRATE, E.G., INTEGRATED CIRCUIT DEVICE (EPO) |
| | E27.002 | Including bulk negative resistance effect component (EPO) |
| | E27.004 | Including solid state component for rectifying, amplifying, or switching without a potential barrier or surface barrier (EPO) |
| | E27.005 | Including component using galvano-magnetic effects, e.g. Hall effect (EPO) |
| | E27.006 | Including piezo-electric, electro-resistive, or magneto-resistive component (EPO) |
| | E27.007 | Including superconducting component (EPO) |
| | E27.008 | Including thermo-electric or thermo-magnetic component with or without a junction of dissimilar material or thermo-magnetic component (EPO) |
| | E27.01 | With semiconductor substrate only (EPO) |
| | E27.011 | Including a plurality of components in a non-repetitive configuration (EPO) |
| | E27.012 | Made of compound semiconductor material, e.g. III-V material (EPO) |
| | E27.013 | Integrated circuit having a two-dimensional layout of components without a common active region (EPO) |
| | E27.014 | Including a field-effect type component (EPO) |
| | E27.015 | In combination with bipolar transistor (EPO) |
| | E27.016 | In combination with diode, resistor, or capacitor (EPO) |
| | E27.017 | In combination with bipolar transistor and diode, resistor, or capacitor (EPO) |
| | E27.018 | With component other than field-effect type (EPO) |
| | E27.019 | Bipolar transistor in combination with diode, capacitor, or resistor (EPO) |
| | E27.02 |  Vertical bipolar transistor in combination with diode, capacitor, or resistor (EPO) |
| | E27.021 |  Vertical bipolar transistor in combination with resistor or capacitor only (EPO) |
| | E27.022 | Vertical bipolar transistor in combination with diode only (EPO) |
| | E27.023 | Lateral bipolar transistor in combination with diode, capacitor, or resistor (EPO) |
| | E27.024 | Including combination of diode, capacitor, or resistor (EPO) |
| | E27.026 | Integrated circuit having a three-dimensional layout (EPO) |
| | E27.028 | Including component having an active region in common (EPO) |
| | E27.029 | Including component of the field-effect type (EPO) |
| | E27.03 | In combination with bipolar transistor and diode, capacitor, or resistor (EPO) |
| | E27.031 | In combination with vertical bipolar transistor and diode, capacitor, or resistor (EPO) |
| | E27.032 | In combination with lateral bipolar transistor and diode, capacitor, or resistor (EPO) |
| | E27.033 | In combination with diode, capacitor, or resistor (EPO) |
| | E27.036 | With component other than field-effect type (EPO) |
| | E27.037 | Bipolar transistor in combination with diode, capacitor, or resistor (EPO) |
| | E27.038 | Vertical bipolar transistor in combination with diode, capacitor, or resistor (EPO) |
| | E27.039 | Vertical bipolar transistor in combination with diode only (EPO) |
| | E27.041 | Vertical bipolar transistor in combination with resistor only (EPO) |
| | E27.042 | Vertical bipolar transistor in combination with capacitor only (EPO) |
| | E27.043 | Lateral bipolar transistor in combination with diode, capacitor, or resistor (EPO) |
| | E27.044 | Including combination of diode, capacitor, or resistor (EPO) |
| | E27.046 | Including only semiconductor components of a single kind, e.g., all bipolar transistors, all diodes, or all CMOS (EPO) |
| | E27.047 | Resistor only (EPO) |
| | E27.048 | Capacitor only (EPO) |
| | E27.051 | Diode only (EPO) |
| | E27.052 | Thyristor only (EPO) |
| | E27.053 | Bipolar component only (EPO) |
| | E27.054 | Combination of lateral and vertical transistors only (EPO) |
| | E27.055 | Vertical bipolar transistor only (EPO) |
| | E27.059 | Including field-effect component only (EPO) |
| | E27.06 | Field-effect transistor with insulated gate (EPO) |
| | E27.061 | Combination of depletion and enhancement field-effect transistors (EPO) |
| | E27.062 | Complementary MIS (EPO) |
| | E27.063 | Means for preventing a parasitic bipolar action between the different transistor regions, e.g. latch-up prevention (EPO) |
| | E27.064 | Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS (EPO) |
| | E27.065 | Including an N-well only in the substrate (EPO) |
| | E27.066 | Including a P-well only in the substrate (EPO) |
| | E27.067 | Including both N- and P- wells in the substrate, e.g. twin-tub (EPO) |
| | E27.068 | Schottky barrier gate field-effect transistor (EPO) |
| | E27.069 | PN junction gate field-effect transistor |
| | E27.07 | Including a plurality of individual components in a repetitive configuration (EPO) |
| | E27.071 | Including resistor or capacitor only (EPO) |
| | E27.072 | Including bipolar component (EPO) |
| | E27.073 | Including diode only (EPO) |
| | E27.074 | Including bipolar transistor (EPO) |
| | E27.075 | Bipolar dynamic random access memory structure (EPO) |
| | E27.076 | Array of single bipolar transistors only, e.g. read only memory structure (EPO) |
| | E27.077 | Static bipolar memory cell structure (EPO) |
| | E27.078 | Bipolar electrically programmable memory structure (EPO) |
| | E27.079 | Thyristor (EPO) |
| | E27.08 | Unijunction transistor, i.e., three terminal device with only one p-n junction having a negative resistance region in the I-V characteristic (EPO) |
| | E27.081 | Including field-effect component (EPO) |
| | E27.082 | Including bucket brigade type charge coupled device (C.C.D) (EPO) |
| | E27.083 | Including charge coupled device (C.C.D) or charge injection device (C.I.D) (EPO) |
| | E27.084 | Dynamic random access memory, DRAM, structure (EPO) |
| | E27.085 | One-transistor memory cell structure, i.e., each memory cell containing only one transistor (EPO) |
| | E27.086 | Storage electrode stacked over the transistor |
| | E27.087 | With bit line higher than capacitor (EPO) |
| | E27.088 | With capacitor higher than bit line level (EPO) |
| | E27.089 | Storage electrode having multiple wings (EPO) |
| | E27.09 | Capacitor extending under the transistor (EPO) |
| | E27.091 | Transistor in trench (EPO) |
| | E27.092 | Capacitor in trench (EPO) |
| | E27.093 | Capacitor extending under or around the transistor (EPO) |
| | E27.094 | Having storage electrode extension stacked over the transistor (EPO) |
| | E27.095 | Capacitor and transistor in common trench (EPO) |
| | E27.097 | Peripheral structure (EPO) |
| | E27.098 | Static random access memory, SRAM, structure (EPO) |
| | E27.102 | Read-only memory, ROM, structure (EPO) |
| | E27.105 | Masterslice integrated circuit (EPO) |
| | E27.111 | Substrate comprising other than a semiconductor material, e.g. insulating substrate or layered substrate Including a non-semiconductor layer (EPO) |
| | E27.114 | Including only passive thin-film or thick-film elements on a common insulating substrate (EPO) |
| | E27.117 | Including organic material in active region |
| | E27.118 | Including semiconductor components sensitive to infrared radiation, light, or electromagnetic radiation of a shorter wavelength (EPO) |
| | E27.119 | Including semiconductor components with at least one potential barrier, surface barrier, or recombination zone adapted for light emission (EPO) |
| | E27.122 | Including active semiconductor component sensitive to infrared radiation, light, or electromagnetic radiation of a shorter wavelength (EPO) |
| | E27.123 | Energy conversion device (EPO) |
| | E27.127 | Device controlled by radiation (EPO) |
| | E27.128 | With at least one potential barrier or surface barrier (EPO) |
| | E27.13 | Imager Including structural or functional details of the device (EPO) |
| | E27.131 | Geometry or disposition of pixel-elements, address-lines, or gate-electrodes (EPO) |
| | E27.132 | Pixel-elements with integrated switching, control, storage, or amplification elements (EPO) |
| | E27.133 | Photodiode array or MOS imager (EPO) |
| | E27.134 | Color imager (EPO) |
| | E27.135 | Multicolor imager having a stacked pixel-element structure, e.g. npn, npnpn or MQW elements (EPO) |
| | E27.136 | Infrared imager (EPO) |
| | E27.137 | Of the hybrid type (e.g., chip-on-chip, bonded substrates) (EPO) |
| | E27.138 | Multispectral infrared imager having a stacked pixel-element structure, e.g., npn, npnpn or MQW structures (EPO) |
| | E27.139 | Anti-blooming (EPO) |
| | E27.14 | X-ray, gamma-ray, or high energy radiation imager (measuring X-, gamma- or corpuscular radiation) (EPO) |
| | E27.141 | Imager using a photoconductor layer (e.g., single photoconductor layer for all pixels) (EPO) |
| | E27.142 | Color imager (EPO) |
| | E27.143 | Infrared imager (EPO) |
| | E27.145 | Anti-blooming (EPO) |
| | E27.146 | X-ray, gamma-ray, or high energy radiation imagers (EPO) |
| | E27.147 | Contact-type imager (e.g., contacts document surface) (EPO) |
| | E27.148 | Junction field effect transistor (JFET) imager or static induction transistor (SIT) imager (EPO) |
| | E27.149 | Bipolar transistor imager (EPO) |
| | E27.15 | Charge coupled imager (EPO) |
| | E27.151 | Structural or functional details (EPO) |
| | E27.153 | Linear CCD imager (EPO) |
| | E27.154 | Area CCD imager (EPO) |
| | E27.155 | Frame-interline transfer (EPO) |
| | E27.156 | Interline transfer (EPO) |
| | E27.157 | Frame transfer (EPO) |
| | E27.158 | Charge injection device (CID) imager (EPO) |
| | E27.159 | CCD or CID color imager (EPO) |
| | E27.16 | Infrared CCD or CID imager (EPO) |
| | E27.162 | Anti-blooming (EPO) |
| | E27.163 | Including a photoconductive layer deposited on the CCD structure (EPO) |
| | E29.001 | SEMICONDUCTORS DEVICES ADAPTED FOR RECTIFYING, AMPLIFYING, OSCILLATING, OR SWITCHING, CAPACITORS, OR RESISTORS WITH AT LEAST ONE POTENTIAL-JUMP BARRIER OR SURFACE BARRIER (EPO) |
| | E29.002 | Electrical characteristics due to properties of entire semiconductor body rather than just surface region (EPO) |
| | E29.003 | Characterized by their crystalline structure (e.g., polycrystalline, cubic) particular orientation of crystalline planes (EPO) |
| | E29.005 | Characterized by specified shape or size of PN junction or by specified impurity concentration gradient within the device (EPO) |
| | E29.006 | Characterized by particular design considerations to control electrical field effect within device (EPO) |
| | E29.007 | For controlling surface leakage or electric field concentration (EPO) |
| | E29.008 | For controlling breakdown voltage of reverse biased devices (EPO) |
| | E29.009 | With field relief electrode (field plate) (EPO) |
| | E29.01 | With at least two field relief electrodes used in combination and not electrically interconnected (EPO) |
| | E29.012 | By doping profile or shape or arrangement of the PN junction, or with supplementary regions (e.g., guard ring, LDD, drift region) (EPO) |
| | E29.013 | With supplementary region doped oppositely to or in rectifying contact with semiconductor containing or contacting region(e.g., guard rings with PN or Schottky junction) (EPO) |
| | E29.014 | With breakdown supporting region for localizing breakdown or limiting its voltage (EPO) |
| | E29.015 | With insulating layer characterized by dielectric or electrostatic property (e.g., including fixed charge or semi-insulating surface layer) (EPO) |
| | E29.016 | For preventing surface leakage due to surface inversion layer (e.g., channel stop) (EPO) |
| | E29.018 | Comprising internal isolation within devices or components (EPO) |
| | E29.022 | Characterized by shape of semiconductor body (EPO) |
| | E29.024 | Characterized by shape, relative sizes or dispositions of semiconductor regions or junctions between regions (EPO) |
| | E29.025 | Characterized by particular shape of junction between semiconductor regions (EPO) |
| | E29.026 | Surface layout of device (EPO) |
| | E29.03 | Emitter regions of bipolar transistors (EPO) |
| | E29.031 | Of lateral transistors (EPO) |
| | E29.032 | Noninterconnected multiemitter structures (EPO) |
| | E29.033 | Of heterojunction bipolar transistors (EPO) |
| | E29.034 | Collector regions of bipolar transistors (EPO) |
| | E29.036 | Anode or cathode regions of thyristors or gated bipolar-mode devices (EPO) |
| | E29.037 | Anode regions of thyristors or gated bipolar-mode devices (EPO) |
| | E29.038 | Cathode regions of thyristors (EPO) |
| | E29.039 | Source or drain regions of field-effect devices (EPO) |
| | E29.04 | Of field-effect transistors with insulated gate (EPO) |
| | E29.041 | Of field-effect transistors with Schottky gate (EPO) |
| | E29.042 | Tunneling barrier (EPO) |
| | E29.044 | Base region of bipolar transistors (EPO) |
| | E29.046 | Base regions of thyristors (EPO) |
| | E29.049 | Channel region of field-effect devices (EPO) |
| | E29.05 | Of field-effect transistors (EPO) |
| | E29.051 | With insulated gate (EPO) |
| | E29.052 | Nonplanar channel (EPO) |
| | E29.053 | With nonuniform doping structure in channel region surface (EPO) |
| | E29.055 | With vertical doping variation (EPO) |
| | E29.056 | With variation of composition of channel (EPO) |
| | E29.057 | With PN junction gate |
| | E29.058 | Of charge coupled devices (EPO) |
| | E29.059 | Gate region of field-effect devices with PN junction gate (EPO) |
| | E29.06 | Substrate region of field-effect devices (EPO) |
| | E29.061 | Of field-effect transistors (EPO) |
| | E29.065 | Of charge coupled devices (EPO) |
| | E29.066 | Body region structure of IGFET's with channel containing layer (DMOSFET or IGBT) (EPO) |
| | E29.068 | Characterized by materials of semiconductor body (EPO) |
| | E29.069 | Single quantum well structures (EPO) |
| | E29.072 | Structures with periodic or quasi-periodic potential variation, (e.g., multiple quantum wells, superlattices) (EPO) |
| | E29.073 | Doping structures (e.g., doping superlattices, nipi-superlattices) (EPO) |
| | E29.074 | Structures without potential periodicity in direction perpendicular to major surface of substrate (e.g., lateral superlattice) (EPO) |
| | E29.075 | Compositional structures (EPO) |
| | E29.079 | Two or more elements from two or more groups of Periodic Table of elements (e.g., alloys) (EPO) |
| | E29.08 | Amorphous materials (EPO) |
| | E29.081 | In different semiconductor regions (e.g., heterojunctions) (EPO) |
| | E29.082 | Only element from fourth group of Periodic System in uncombined form (EPO) |
| | E29.083 | Amorphous materials (EPO) |
| | E29.084 | Including two or more of elements from fourth group of Periodic System (EPO) |
| | E29.086 | Further characterized by doping material (EPO) |
| | E29.087 | Selenium or tellurium only (EPO) |
| | E29.089 | Only Group III-V compounds (EPO) |
| | E29.09 | Including two or more compounds (e.g., alloys) (EPO) |
| | E29.092 | Amorphous materials (EPO) |
| | E29.093 | Further characterized by doping material (EPO) |
| | E29.094 | Only Group II-VI compounds (EPO) |
| | E29.095 | Amorphous materials (EPO) |
| | E29.096 | Including two or more compounds (e.g., alloys) (EPO) |
| | E29.098 | Further characterized by doping material (EPO) |
| | E29.099 | CdX compounds being one element of sixth group of Periodic System (EPO) |
| | E29.1 | Semiconductor materials other than Group IV, selenium, tellurium, or Group III-V compounds (EPO) |
| | E29.105 | Characterized by combinations of two or more features of crystalline structure, shape, materials, physical imperfections, and concentration/distribution of impurities in bulk material (EPO) |
| | E29.106 | Characterized by physical imperfections; having polished or roughened surface (EPO) |
| | E29.107 | Imperfections within semiconductor body (EPO) |
| | E29.108 | Imperfections on surface of semiconductor body (EPO) |
| | E29.109 | Characterized by concentration or distribution of impurities in bulk material (EPO) |
| | E29.111 | Electrodes (EPO) |
| | E29.112 | Characterized by their shape, relative sizes or dispositions (EPO) |
| | E29.113 | Carrying current to be rectified, amplified or switched (EPO) |
| | E29.114 | Emitter or collector electrodes for bipolar transistors (EPO) |
| | E29.115 | Cathode or anode electrodes for thyristors (EPO) |
| | E29.116 | Source or drain electrodes for field-effect devices (EPO) |
| | E29.117 | For thin film transistors with insulated gate (EPO) |
| | E29.118 | For vertical current flow (EPO) |
| | E29.119 | For lateral devices where connection to source or drain region is done through at least one part of semiconductor substrate thickness (e.g., with connecting sink or with via-hole) (EPO) |
| | E29.12 | Layout configuration for lateral device source or drain region (e.g., cellular, interdigitated or ring structure or being curved or angular) (EPO) |
| | E29.121 | Source or drain electrode in groove (EPO) |
| | E29.122 | Characterized by relative position of source or drain electrode and gate electrode (EPO) |
| | E29.123 | Not carrying current to be rectified, amplified, or switched (EPO) |
| | E29.124 | Base electrodes for bipolar transistors (EPO) |
| | E29.125 | Gate electrodes for thyristors (EPO) |
| | E29.126 | Gate stack for field-effect devices (EPO) |
| | E29.127 | For field-effect transistors (EPO) |
| | E29.128 | With insulated gate (EPO) |
| | E29.129 | Gate electrodes for transistors with floating gate (EPO) |
| | E29.13 | Gate electrodes for nonplanar MOSFET (EPO) |
| | E29.131 | Having drain and source regions at different vertical level having channel composed only of vertical sidewall connecting drain and source layers (EPO) |
| | E29.132 | Characterized by insulating layer (EPO) |
| | E29.134 | Characterized by configuration of gate electrode layer (EPO) |
| | E29.135 | Characterized by length or sectional shape (EPO) |
| | E29.136 | Characterized by surface lay-out (EPO) |
| | E29.137 | Characterized by configuration of gate stack of thin film FETs (EPO) |
| | E29.138 | For charge coupled devices (EPO) |
| | E29.139 | Of specified material (EPO) |
| | E29.14 | For gate of heterojunction field-effect devices (EPO) |
| | E29.141 | Resistive materials for field-effect devices (EPO) |
| | E29.142 | Superconductor materials (EPO) |
| | E29.143 | Ohmic electrodes (EPO) |
| | E29.148 | Schottky barrier electrodes (EPO) |
| | E29.15 | Electrodes for IGFET (EPO) |
| | E29.151 | For TFT (EPO) |
| | E29.154 | Silicon gate conductor material (EPO) |
| | E29.158 | Elemental metal gate conductor material (e.g., W, Mo) (EPO) |
| | E29.16 | Gate conductor material being compound or alloy material (e.g., organic material, TiN, MoSi 2 ) (EPO) |
| | E29.162 | Insulating materials for IGFET (EPO) |
| | E29.166 | Types of semiconductor device (EPO) |
| | E29.167 | Controllable by plural effects that include variations in magnetic field, mechanical force, or electric current/potential applied to device or one or more electrodes of device (EPO) |
| | E29.168 | Quantum effect device (EPO) |
| | E29.169 | Controllable by only signal applied to control electrode (e.g., base of bipolar transistor, gate of field-effect transistor) (EPO) |
| | E29.17 | Memory effect devices (EPO) |
| | E29.171 | Bipolar device (EPO) |
| | E29.172 | Double-base diode (EPO) |
| | E29.173 | Transistor-type device (i.e., able to continuously respond to applied control signal) |
| | E29.174 | Bipolar junction transistor |
| | E29.175 | Structurally associated with other devices (EPO) |
| | E29.176 | Device being resistive element (e.g., ballasting resistor) (EPO) |
| | E29.177 | Point contact transistors (EPO) |
| | E29.178 | Schottky transistors (EPO) |
| | E29.179 | Tunnel transistors (EPO) |
| | E29.18 | Avalanche transistors (EPO) |
| | E29.181 | Transistors with hook collector (i.e., collector having two layers of opposite conductivity type (e.g., SCR)) (EPO) |
| | E29.182 | Bipolar thin-film transistors (EPO) |
| | E29.183 | Vertical transistor (EPO) |
| | E29.184 | Having emitter-base and base-collector junctions in same plane (EPO) |
| | E29.185 | Having emitter-base junction and base-collector junction on different surfaces (e.g., mesa planar transistor) (EPO) |
| | E29.186 | Inverse vertical transistor (EPO) |
| | E29.187 | Lateral transistor (EPO) |
| | E29.188 | Hetero-junction transistor (EPO) |
| | E29.189 | Vertical transistors (EPO) |
| | E29.19 | Having two-dimensional base (e.g., modulation-doped base, inversion layer base, delta-doped base) (EPO) |
| | E29.191 | Having emitter comprising one or more nonmonocrystalline elements of Group IV (e.g., amorphous silicon) alloys comprising Group IV elements (EPO) |
| | E29.192 | Resonant tunneling transistors (EPO) |
| | E29.193 | Comprising lattice mismatched active layers (e.g., SiGe strained layer transistors) (EPO) |
| | E29.194 | Controlled by field effect (e.g., bipolar static induction transistor (BSIT)) (EPO) |
| | E29.195 | Gated diode structure (EPO) |
| | E29.196 | With PN junction gate (e.g., field-controlled thyristor (FCTh), static induction thyristor (SITh)) (EPO) |
| | E29.197 | Insulated gate bipolar mode transistor (e.g., IGBT; IGT; COMFET) (EPO) |
| | E29.198 | Transistor with vertical current flow (EPO) |
| | E29.199 | With both emitter and collector contacts in same substrate side (EPO) |
| | E29.202 | Thin-film device (EPO) |
| | E29.211 | Thyristor-type device (e.g., having four-zone regenerative action) (EPO) |
| | E29.212 | Gate-turn-off device (EPO) |
| | E29.215 | Bidirectional device (e.g., triac) (EPO) |
| | E29.216 | With turn on by field effect (EPO) |
| | E29.217 | Combined structurally with at least one other device (EPO) |
| | E29.218 | Combined with capacitor or resistor (EPO) |
| | E29.219 | Combined with diode (EPO) |
| | E29.221 | Combined with field-effect transistor (EPO) |
| | E29.222 | Having built-in localized breakdown/breakover region (EPO) |
| | E29.223 | Having amplifying gate structure (e.g., Darlington configuration) (EPO) |
| | E29.224 | Asymmetrical thyristor (EPO) |
| | E29.225 | Lateral thyristor (EPO) |
| | E29.226 | Unipolar device (EPO) |
| | E29.227 | Charge transfer device (EPO) |
| | E29.228 | Charge-coupled device (EPO) |
| | E29.241 | Hot electron transistor (HET) or metal base transistor (MBT) (EPO) |
| | E29.242 | Field-effect transistor (EPO) |
| | E29.243 | Using static field induced region (e.g., SIT, PBT) (EPO) |
| | E29.244 | Velocity modulations transistor (i.e., VMT) (EPO) |
| | E29.245 | With one-dimensional charge carrier gas channel (e.g., quantum wire FET) (EPO) |
| | E29.246 | With two-dimensional charge carrier gas channel (e.g., HEMT; with two-dimensional charge-carrier layer formed at heterojunction interface) (EPO) |
| | E29.247 | With inverted single heterostructure (i.e., with active layer formed on top of wide bandgap layer (e.g., IHEMT)) (EPO) |
| | E29.248 | With confinement of carriers by at least two heterojunctions (e.g., DHHEMT, quantum well HEMT, DHMODFET) (EPO) |
| | E29.252 | With direct single heterostructure (i.e., with wide bandgap layer formed on top of active layer (e.g., direct single heterostructure MIS-like HEMT)) (EPO) |
| | E29.254 | With delta-doped channel (EPO) |
| | E29.255 | With field effect produced by insulated gate (EPO) |
| | E29.256 | With channel containing layer contacting drain drift region (e.g., DMOS transistor) (EPO) |
| | E29.257 | Having vertical bulk current component or current vertically following trench gate (e.g., vertical power DMOS transistor) (EPO) |
| | E29.258 | With both source and drain contacts in same substrate side (EPO) |
| | E29.259 | With nonplanar surface (EPO) |
| | E29.261 | With at least part of active region on insulating substrate (e.g., lateral DMOS in oxide isolated well) (EPO) |
| | E29.262 | Vertical transistor (EPO) |
| | E29.263 | Comprising gate-to-body connection (i.e., bulk dynamic threshold voltage MOSFET) (EPO) |
| | E29.264 | With multiple gate structure (EPO) |
| | E29.265 | Structure comprising MOS gate and at least one non-MOS gate (e.g., JFET or MESFET gate) (EPO) |
| | E29.266 | With lightly doped drain or source extension (EPO) |
| | E29.267 | With nonplanar structure (e.g., gate or source or drain being nonplanar) (EPO) |
| | E29.268 | Source region and drain region having nonsymmetrical structure about gate electrode (EPO) |
| | E29.269 | With overlap between lightly doped extension and gate electrode (EPO) |
| | E29.27 | With buried channel (EPO) |
| | E29.271 | With Schottky drain or source contact (EPO) |
| | E29.272 | Gate comprising ferroelectric layer (EPO) |
| | E29.273 | Thin-film transistor (EPO) |
| | E29.274 | Vertical transistor (EPO) |
| | E29.275 | With multiple gates (EPO) |
| | E29.276 | With supplementary region or layer in thin film or in insulated bulk substrate supporting it for controlling or increasing voltage resistance of device (EPO) |
| | E29.277 | Characterized by drain or source properties (EPO) |
| | E29.28 | For preventing leakage current (EPO) |
| | E29.281 | For preventing kink or snapback effect (e.g., discharging minority carriers of channel region for preventing bipolar effect) (EPO) |
| | E29.282 | With light shield (EPO) |
| | E29.283 | With supplementary region or layer for improving flatness of device (EPO) |
| | E29.284 | With drain or source connected to bulk conducting substrate (EPO) |
| | E29.285 | Silicon transistor (EPO) |
| | E29.295 | Characterized by insulating substrate or support (EPO) |
| | E29.296 | Comprising Group III-V or II-VI compound, or of Se, Te, or oxide semiconductor (EPO) |
| | E29.297 | Comprising Group IV non-Si semiconductor materials or alloys (e.g., Ge, SiN alloy, SiC alloy) (EPO) |
| | E29.299 | Characterized by property or structure of channel or contact thereto (EPO) |
| | E29.3 | With floating gate (EPO) |
| | E29.301 | Programmable by two single electrons (EPO) |
| | E29.302 | Hi-lo programming levels only (EPO) |
| | E29.303 | Charging by injection of carriers through conductive insulator (e.g., Poole-Frankel conduction) (EPO) |
| | E29.304 | Charging by tunneling of carriers (e.g., Fowler-Nordheim tunneling) (EPO) |
| | E29.305 | Charging by hot carrier injection (EPO) |
| | E29.308 | Programmable with more than two possible different levels (EPO) |
| | E29.309 | With charge trapping gate insulator (e.g., MNOS-memory transistors) (EPO) |
| | E29.31 | With field effect produced by PN or other rectifying junction gate (i.e., potential barrier) (EPO) |
| | E29.322 | Single electron transistors: Coulomb blockade device (EPO) |
| | E29.323 | Controllable by variation of magnetic field applied to device (EPO) |
| | E29.324 | Controllable by variation of applied mechanical force (e.g., of pressure) (EPO) |
| | E29.325 | Controllable only by variation of electric current supplied or only electric potential applied to electrode carrying current to be rectified, amplified, oscillated, or switched (EPO) |
| | E29.326 | Resistor with PN junction (EPO) |
| | E29.327 | Diode (EPO) |
| | E29.328 | Planar PN junction diode (EPO) |
| | E29.329 | Mesa PN junction diode (EPO) |
| | E29.33 | Hi-lo semiconductor device (e.g., memory device) (EPO) |
| | E29.331 | Charge trapping diode (EPO) |
| | E29.332 | Punchthrough diode (i.e., with bulk potential barrier (e.g., camel diode, planar doped barrier diode, graded bandgap diode)) (EPO) |
| | E29.333 | Point contact diode (EPO) |
| | E29.334 | Transit-time diode (e.g., IMPATT, TRAPATT diode) (EPO) |
| | E29.335 | Avalanche diode (e.g., Zener diode) (EPO) |
| | E29.336 | PIN diode (EPO) |
| | E29.337 | Thyristor diode (i.e., having only two terminals and no control electrode (e.g., Shockley diode, break-over diode)) (EPO) |
| | E29.338 | Schottky diode (EPO) |
| | E29.339 | Tunneling diode (EPO) |
| | E29.342 | Capacitor with potential barrier or surface barrier (EPO) |
| | E29.347 | Controllable by thermal signal (e.g., IR) (EPO) |
| | E45.001 | SOLID-STATE DEVICES ADAPTED FOR RECTIFYING, AMPLIFYING, OSCILLATING, OR SWITCHING WITHOUT POTENTIAL-JUMP BARRIER OR SURFACE BARRIER, E.G., DIELECTRIC TRIODES; OVSHINSKY-EFFECT DEVICES, PROCESSES, OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT THEREOF, OR OF PARTS THEREOF (EPO) |
| | E45.002 | Bistable switching devices, e.g., Ovshinsky-effect devices (EPO) |
| | E45.003 | Switching materials being oxides or nitrides (EPO) |
| | E45.004 | N: Light-controlled Ovshinsky devices (EPO) |
| | E45.005 | Charge density wave transport devices (EPO) |
| | E45.006 | Solid-state travelling-wave devices (EPO) |
| | E25.001 | ASSEMBLIES CONSISTING OF PLURALITY OF INDIVIDUAL SEMICONDUCTOR OR OTHER SOLID-STATE DEVICES (EPO) |
| | E25.002 | All devices being of same type, e.g., assemblies of rectifier diodes (EPO) |
| | E25.003 | Devices not having separate containers (EPO) |
| | E25.005 | Devices being arranged next to each other (EPO) |
| | E25.006 | Stacked arrangements of devices (EPO) |
| | E25.008 | Organic solid-state devices (EPO) |
| | E25.01 | Device consisting of plurality of semiconductor or other solid state devices or components formed in or on common substrate, e.g., integrated circuit device (EPO) |
| | E25.011 | Devices being arranged next and on each other, i.e., mixed assemblies (EPO) |
| | E25.012 | Devices being arranged next to each other (EPO) |
| | E25.013 | Stacked arrangements of devices (EPO) |
| | E25.014 | Semiconductor devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (EPO) |
| | E25.015 | Devices being arranged next and on each other, i.e., mixed assemblies (EPO) |
| | E25.016 | Devices being arranged next to each other (EPO) |
| | E25.017 | Apertured devices mounted on one or more rods passed through apertures (EPO) |
| | E25.018 | Stacked arrangements of nonapertured devices (EPO) |
| | E25.019 | Incoherent light-emitting semiconductor devices having potential or surface barrier (EPO) |
| | E25.022 | Devices having separate containers (EPO) |
| | E25.023 | Device consisting of plurality of semiconductor or other solid-state devices or components formed in or on common substrate, e.g., integrated circuit device (EPO) |
| | E25.024 | Semiconductors devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (EPO) |
| | E25.025 | Mixed assemblies (EPO) |
| | E25.026 | Devices being arranged next to each other (EPO) |
| | E25.027 | Stacked arrangements of devices (EPO) |
| | E25.028 | Incoherent light-emitting semiconductor devices having potential or surface barrier (EPO) |
| | E25.029 | Devices being of two or more types, e.g., forming hybrid circuits (EPO) |
| | E23.001 | PACKAGING, INTERCONNECTS, AND MARKINGS FOR SEMICONDUCTOR OR OTHER SOLID-STATE DEVICES (EPO) |
| | E23.002 | Details not otherwise provided for, e.g., protection against moisture (EPO) |
| | E23.003 | Mountings, e.g., nondetachable insulating substrates (EPO) |
| | E23.004 | Characterized by shape (EPO) |
| | E23.005 | Characterized by material or its electrical properties (EPO) |
| | E23.01 | Arrangements for conducting electric current to or from solid-state body in operation, e.g., leads, terminal arrangements (EPO) |
| | E23.011 | Internal lead connections, e.g., via connections, feedthrough structures (EPO) |
| | E23.012 | Consisting of lead-in layers inseparably applied to semiconductor body (EPO) |
| | E23.013 | Bridge structure with air gap (EPO) |
| | E23.014 | Beam leads (EPO) |
| | E23.015 | Pads with extended contours, e.g., grid structure, branch structure, finger structure (EPO) |
| | E23.016 | For devices consisting of semiconductor layers on insulating or semi-insulating substrates, e.g., silicon on sapphire devices, i.e., SOS (EPO) |
| | E23.017 | Materials (EPO) |
| | E23.019 | Consisting of layered constructions comprising conductive layers and insulating layers, e.g., planar contacts (EPO) |
| | E23.023 | Consisting of soldered or bonded constructions (EPO) |
| | E23.024 | Wire-like arrangements or pins or rods (EPO) |
| | E23.026 | Bases or plates or solder therefor (EPO) |
| | E23.031 | Lead frames or other flat leads (EPO) |
| | E23.032 | Additional leads (EPO) |
| | E23.033 | Additional leads being bump or wire (EPO) |
| | E23.034 | Additional leads being tape carrier or flat leads (EPO) |
| | E23.035 | Additional leads being multilayer (EPO) |
| | E23.036 | Additional leads being wiring board (EPO) |
| | E23.037 | Characterized by die pad (EPO) |
| | E23.038 | Insulative substrate being used as die pad, e.g., ceramic, plastic (EPO) |
| | E23.039 | Chip-on-leads or leads-on-chip techniques, i.e., inner lead fingers being used as die pad (EPO) |
| | E23.04 | Having bonding material between chip and die pad (EPO) |
| | E23.041 | Multilayer (EPO) |
| | E23.042 | Plurality of lead frames mounted in one device (EPO) |
| | E23.043 | Geometry of lead frame (EPO) |
| | E23.044 | For devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (EPO) |
| | E23.045 | Deformation absorbing parts in lead frame plane, e.g., meanderline shape (EPO) |
| | E23.046 | Cross-section geometry (EPO) |
| | E23.049 | Insulating layers on lead frame, e.g., bridging members (EPO) |
| | E23.051 | Specifically adapted to facilitate heat dissipation (EPO) |
| | E23.052 | Assembly of semiconductor devices on lead frame (EPO) |
| | E23.053 | Characterized by materials of lead frames or layers thereon (EPO) |
| | E23.055 | Consisting of thin flexible metallic tape with or without film carrier (EPO) |
| | E23.056 | Insulating layers on lead frames (EPO) |
| | E23.057 | Capacitor integral with or on lead frame (EPO) |
| | E23.058 | Battery in combination with lead frame (EPO) |
| | E23.059 | Oscillators in combination with lead frame (EPO) |
| | E23.06 | Leads, i.e., metallizations or lead frames on insulating substrates, e.g., chip carriers (EPO) |
| | E23.061 | Leads being also applied on sidewalls or bottom of substrate, e.g., leadless packages for surface mounting (EPO) |
| | E23.062 | Multilayer substrates (EPO) |
| | E23.063 | Chip support structure consisting of plurality of insulating substrates (EPO) |
| | E23.064 | For flat cards, e.g., credit cards (EPO) |
| | E23.065 | Flexible insulating substrates (EPO) |
| | E23.066 | Lead frames fixed on or encapsulated in insulating substrates (EPO) |
| | E23.067 | Via connections through substrates, e.g., pins going through substrate, coaxial cables (EPO) |
| | E23.068 | Additional leads joined to metallizations on insulating substrate, e.g., pins, bumps, wires, flat leads (EPO) |
| | E23.07 | Geometry or layout (EPO) |
| | E23.071 | For devices adapted for rectifying, amplifying, oscillating, or switching, capacitors, or resistors with at least one potential-jump barrier or surface barrier (EPO) |
| | E23.072 | Characterized by materials (EPO) |
| | E23.073 | Conductive materials containing semiconductor material (EPO) |
| | E23.074 | Carbon, e.g., fullerenes (EPO) |
| | E23.075 | Conductive materials containing organic materials or pastes, e.g., for thick films (EPO) |
| | E23.076 | Conductive materials containing superconducting material (EPO) |
| | E23.077 | Materials of insulating layers or coatings (EPO) |
| | E23.078 | Flexible arrangements, e.g., pressure contacts without soldering (EPO) |
| | E23.079 | For integrated circuit devices, e.g., power bus, number of leads (EPO) |
| | E23.08 | Arrangements for cooling, heating, ventilating or temperature compensation; temperature-sensing arrangements (EPO) |
| | E23.081 | Arrangements for heating (EPO) |
| | E23.082 | Cooling arrangements using Peltier effect (EPO) |
| | E23.083 | Mountings or securing means for detachable cooling or heating arrangements; fixed by friction, plugs or springs (EPO) |
| | E23.087 | Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling (EPO) |
| | E23.088 | Cooling by change of state, e.g., use of heat pipes (EPO) |
| | E23.09 | Auxiliary members in containers characterized by their shape, e.g., pistons (EPO) |
| | E23.095 | Complete device being wholly immersed in fluid other than air (EPO) |
| | E23.097 | Involving transfer of heat by flowing fluids (EPO) |
| | E23.101 | Selection of materials, or shaping, to facilitate cooling or heating, e.g., heat sinks (EPO) |
| | E23.102 | Cooling facilitated by shape of device (EPO) |
| | E23.103 | Foil-like cooling fins or heat sinks (EPO) |
| | E23.104 | Characterized by shape of housing (EPO) |
| | E23.105 | Wire-like or pin-like cooling fins or heat sinks (EPO) |
| | E23.106 | Laminates or multilayers, e.g., direct bond copper ceramic substrates (EPO) |
| | E23.107 | Organic materials with or without thermo-conductive filler (EPO) |
| | E23.108 | Semiconductor materials (EPO) |
| | E23.109 | Metallic materials (EPO) |
| | E23.11 | Cooling facilitated by selection of materials for device (or materials for thermal expansion adaptation, e.g., carbon) (EPO) |
| | E23.114 | Protection against radiation, e.g., light, electromagnetic waves (EPO) |
| | E23.116 | Encapsulations, e.g., encapsulating layers, coatings, e.g., for protection (EPO) |
| | E23.117 | Characterized by material, e.g., carbon (EPO) |
| | E23.118 | Oxides or nitrides or carbides, e.g., ceramics, glass (EPO) |
| | E23.119 | Organic, e.g., plastic, epoxy (EPO) |
| | E23.122 | Semiconductor material, e.g., amorphous silicon (EPO) |
| | E23.123 | Characterized by arrangement or shape (EPO) |
| | E23.124 | Device being completely enclosed (EPO) |
| | E23.125 | Substrate forming part of encapsulation (EPO) |
| | E23.126 | Double encapsulation or coating and encapsulation (EPO) |
| | E23.127 | Sealing arrangements between parts, e.g., adhesion promoters (EPO) |
| | E23.128 | Encapsulation having cavity (EPO) |
| | E23.129 | Partial encapsulation or coating (EPO) |
| | E23.135 | Fillings or auxiliary members in containers or encapsulations, e.g., centering rings (EPO) |
| | E23.136 | Fillings characterized by material, its physical or chemical properties, or its arrangement within complete device (EPO) |
| | E23.137 | Including materials for absorbing or reacting with moisture or other undesired substances, e.g., getters (EPO) |
| | E23.138 | Gaseous at normal operating temperature of device (EPO) |
| | E23.139 | Liquid at normal operating temperature of device (EPO) |
| | E23.14 | Solid or gel at normal operating temperature of device (EPO) |
| | E23.141 | Arrangements for conducting electric current within device in operation from one component to another, interconnections, e.g., wires, lead frames (EPO) |
| | E23.142 | Including external interconnections consisting of multilayer structure of conductive and insulating layers inseparably formed on semiconductor body (EPO) |
| | E23.143 | Crossover interconnections (EPO) |
| | E23.144 | Capacitive arrangements or effects of, or between wiring layers (EPO) |
| | E23.145 | Via connections in multilevel interconnection structure (EPO) |
| | E23.146 | With adaptable interconnections (EPO) |
| | E23.147 | Comprising antifuses, i.e., connections having their state changed from nonconductive to conductive (EPO) |
| | E23.149 | Comprising fuses, i.e., connections having their state changed from conductive to nonconductive (EPO) |
| | E23.151 | Geometry or layout of interconnection structure (EPO) |
| | E23.154 | Characterized by materials (EPO) |
| | E23.155 | Conductive materials (EPO) |
| | E23.156 | Containing superconducting materials (EPO) |
| | E23.157 | Based on metals, e.g., alloys, metal silicides (EPO) |
| | E23.158 | Principal metal being aluminum (EPO) |
| | E23.159 | Aluminum alloys (EPO) |
| | E23.16 | Additional layers associated with aluminum layers, e.g., adhesion, barrier, cladding layers (EPO) |
| | E23.161 | Principal metal being copper (EPO) |
| | E23.162 | Principal metal being noble metal, e.g., gold (EPO) |
| | E23.163 | Principal metal being refractory metal (EPO) |
| | E23.164 | Containing semiconductor material, e.g., polysilicon (EPO) |
| | E23.165 | Containing carbon, e.g., fullerenes (EPO) |
| | E23.166 | Containing conductive organic materials or pastes, e.g., conductive adhesives, inks (EPO) |
| | E23.167 | Insulating materials (EPO) |
| | E23.168 | Including internal interconnections, e.g., cross-under constructions (EPO) |
| | E23.169 | Interconnection structure between plurality of semiconductor chips being formed on or in insulating substrates (EPO) |
| | E23.17 | Crossover interconnections, e.g., bridge stepovers (EPO) |
| | E23.171 | Adaptable interconnections, e.g., for engineering changes (EPO) |
| | E23.172 | Assembly of plurality of insulating substrates (EPO) |
| | E23.173 | Multilayer substrates (EPO) |
| | E23.174 | Conductive vias through substrate with or without pins, e.g., buried coaxial conductors (EPO) |
| | E23.175 | Geometry or layout of interconnection structure (EPO) |
| | E23.176 | For flat cards, e.g., credit cards (EPO) |
| | E23.177 | Flexible insulating substrates (EPO) |
| | E23.178 | Chips being integrally enclosed by interconnect and support structures (EPO) |
| | E23.179 | Marks applied to semiconductor devices or parts, e.g., registration marks, test patterns, alignment structures, wafer maps (EPO) |
| | E23.18 | Containers; seals (EPO) |
| | E23.181 | Characterized by shape of container or parts, e.g., caps, walls (EPO) |
| | E23.182 | Container being hollow construction having no base used as mounting for semiconductor body (EPO) |
| | E23.183 | Container being hollow construction and having conductive base as mounting as well as lead for the semiconductor body (EPO) |
| | E23.184 | Other leads having insulating passage through base (EPO) |
| | E23.185 | Other leads being parallel to base (EPO) |
| | E23.186 | Other leads being perpendicular to base (EPO) |
| | E23.187 | Another lead being formed by cover plate parallel to base plate, e.g., sandwich type (EPO) |
| | E23.188 | Container being hollow construction and having insulating or insulated base as mounting for semiconductor body (EPO) |
| | E23.191 | Characterized by material of container or its electrical properties (EPO) |
| | E23.193 | Characterized by material or arrangement of seals between parts, e.g., between cap and base of container or between leads and walls of container (EPO) |
| | E23.194 | Protection against mechanical damage (EPO) |
| | E49.001 | SOLID-STATE DEVICES WITH AT LEAST ONE POTENTIAL-JUMP BARRIER OR SURFACE BARRIER USING ACTIVE LAYER OF LOWER ELECTRICAL CONDUCTIVITY THAN MATERIAL ADJACENT THERETO AND THROUGH WHICH CARRIER TUNNELING OCCURS, PROCESSES OR APPARATUS PECULIAR TO MANUFACTURE OR TREATMENT OF SUCH DEVICES, OR OF PARTS THEREOF (EPO) |
| | E49.002 | Devices using Mott metal-insulator transition, e.g., field-effect transistors (EPO) |
| | E49.003 | Quantum devices, e.g., quantum interference devices, metal single electron transistor (EPO) |
| | E49.004 | Thin-film or thick-film devices (EPO) |
| | E21.001 | PROCESSES OR APPARATUS ADAPTED FOR MANUFACTURE OR TREATMENT OF SEMICONDUCTOR OR SOLID-STATE DEVICES OR OF PARTS THEREOF (EPO) |
| | E21.002 | Manufacture or treatment of semiconductor device (EPO) |
| | E21.003 | Manufacture of two-terminal component for integrated circuit (EPO) |
| | E21.004 | Of resistor (EPO) |
| | E21.005 | Active material comprising carbon, e.g., diamond or diamond-like carbon (EPO) |
| | E21.006 | Active material comprising refractory, transition, or noble metal or metal compound, e.g., alloy, silicide, oxide, nitride (EPO) |
| | E21.007 | Active material comprising organic conducting material, e.g., conducting polymer (EPO) |
| | E21.008 | Of capacitor (EPO) |
| | E21.009 | Dielectric having perovskite structure (EPO) |
| | E21.01 | Dielectric comprising two or more layers, e.g., buffer layers, seed layers, gradient layers (EPO) |
| | E21.011 | Formation of electrode (EPO) |
| | E21.012 | With increased surface area, e.g., by roughening, texturing (EPO) |
| | E21.013 | With rough surface, e.g., using hemispherical grains (EPO) |
| | E21.014 | Having cylindrical, crown, or fin-type shape (EPO) |
| | E21.015 | Having horizontal extensions (EPO) |
| | E21.016 | Made by depositing layers, e.g., alternatingly conductive and insulating layers (EPO) |
| | E21.017 | Made by patterning layers, e.g., etching conductive layers (EPO) |
| | E21.018 | Having vertical extensions (EPO) |
| | E21.019 | Made by depositing layers, e.g., alternatingly conductive and insulating layers (EPO) |
| | E21.02 | Made by patterning layers, e.g., etching conductive layers (EPO) |
| | E21.021 | Having multilayers, e.g., comprising barrier layer and metal layer (EPO) |
| | E21.022 | Of inductor (EPO) |
| | E21.023 | Making mask on semicond uctor body for further photolithographic processing (EPO) |
| | E21.024 | Comprising organic layer (EPO) |
| | E21.033 | Comprising inorganic layer (EPO) |
| | E21.034 | For lift-off process (EPO) |
| | E21.035 | Characterized by their composition, e.g., multilayer masks, materials (EPO) |
| | E21.036 | Characterized by their size, orientation, disposition, behavior, shape, in horizontal or vertical plane (EPO) |
| | E21.037 | Characterized by their behavior during process, e.g., soluble mask, re-deposited mask (EPO) |
| | E21.038 | Characterized by process involved to create mask, e.g., lift-off mask, sidewalls, or to modify mask, such as pre-treatment, post-treatment (EPO) |
| | E21.039 | Process specially adapted to improve the resolution of the mask (EPO) |
| | E21.04 | Device having at least one potential-jump barrier or surface barrier, e.g., PN junction, depletion layer, carrier concentration layer (EPO) |
| | E21.041 | Device having semiconductor body comprising carbon, e.g., diamond, diamond-like carbon (EPO) |
| | E21.042 | Making n- or p-doped regions (EPO) |
| | E21.044 | Changing their shape, e.g., forming recess (EPO) |
| | E21.045 | Making electrode (EPO) |
| | E21.046 | Ohmic electrode (EPO) |
| | E21.047 | Schottky electrode (EPO) |
| | E21.048 | Conductor-insulator-semiconductor electrode, e.g., MIS contacts (EPO) |
| | E21.049 | Multistep processes for manufacture of device whose active layer, e.g., base, channel, comprises semiconducting carbon, e.g., diamond, diamond-like carbon (EPO) |
| | E21.054 | Device having semiconductor body comprising silicon carbide (SiC) (EPO) |
| | E21.055 | Passivating silicon carbide surface (EPO) |
| | E21.056 | Making n- or p- doped regions or layers, e.g., using diffusion (EPO) |
| | E21.06 | Changing shape of semiconductor body, e.g., forming recesses (EPO) |
| | E21.061 | Making electrode (EPO) |
| | E21.062 | Ohmic electrode (EPO) |
| | E21.063 | Conductor-insulator-semiconductor electrode, e.g., MIS contact (EPO) |
| | E21.064 | Schottky electrode (EPO) |
| | E21.065 | Multistep processes for manufacture of device whose active layer, e.g., base, channel, comprises silicon carbide (EPO) |
| | E21.068 | Device having semiconductor body comprising selenium (Se) or tellurium (Te) (EPO) |
| | E21.069 | Preparation of substrate or foundation plate for Se or Te semiconductor (EPO) |
| | E21.07 | Preliminary treatment of Se or Te, its application to substrate, or the subsequent treatment of combination (EPO) |
| | E21.071 | Application of Se or Te to substrate or foundation plate (EPO) |
| | E21.072 | Conversion of Se or Te to conductive state (EPO) |
| | E21.073 | Treatment of surface of Se or Te layer after having been made conductive (EPO) |
| | E21.074 | Provision of discrete insulating layer, i.e., specified barrier layer material (EPO) |
| | E21.075 | Application of electrode to exposed surface of Se or Te after Se or Te has been applied to foundation plate (EPO) |
| | E21.076 | Treatment of complete device, e.g., by electroforming to form barrier (EPO) |
| | E21.078 | Device having semiconductor body comprising cuprous oxide (Cu 2 O) or cuprous iodide (CuI) (EPO) |
| | E21.079 | Preparation of substrate, preliminary treatment oxidation of substrate, reduction treatment (EPO) |
| | E21.08 | Preliminary treatment of foundation plate (EPO) |
| | E21.081 | Reduction of copper oxide, treatment of oxide layer (EPO) |
| | E21.082 | Oxidation and subsequent heat treatment of substrate (EPO) |
| | E21.083 | Application of specified conductive layer (EPO) |
| | E21.084 | Treatment of complete device, e.g., electroforming, heat treating (EPO) |
| | E21.085 | Device having semiconductor body comprising Group IV elements or Group III-V compounds with or without impurities, e.g., doping materials (EPO) |
| | E21.086 | Intermixing or interdiffusion or disordering of Group III-V heterostructures, e.g., IILD (EPO) |
| | E21.087 | Joining of semiconductor body for junction formation (EPO) |
| | E21.089 | Multistep processes for manufacture of device using quantum interference effect, e.g., electrostatic Aharonov-Bohm effect (EPO) |
| | E21.09 | Deposition of semiconductor material on substrate, e.g., epitaxial growth, solid phase epitaxy (EPO) |
| | E21.091 | Using physical deposition, e.g., vacuum deposition, sputtering (EPO) |
| | E21.092 | Epitaxial deposition of Group IV element, e.g., Si, Ge (EPO) |
| | E21.093 | Deposition on semiconductor substrate being different from deposited semiconductor material; i.e., formation of heterojunctions (EPO) |
| | E21.094 | Deposition on insulating or meta llic substrate (EPO) |
| | E21.095 | Epitaxial deposition of diamond (EPO) |
| | E21.096 | Deposition of diamond (EPO) |
| | E21.097 | Epitaxial deposition of Group III-V compound (EPO) |
| | E21.101 | Using reduction or decomposition of gaseous compound yielding solid condensate, i.e., chemical deposition (EPO) |
| | E21.102 | Epitaxial deposition of Group IV elements, e.g., Si, Ge, C (EPO) |
| | E21.103 | Deposition on a semiconductor substrate which is different from the semiconductor material being deposited, i.e., formation of heterojunctions (EPO) |
| | E21.104 | Deposition on an insulating or a metallic substrate (EPO) |
| | E21.105 | Epitaxial deposition of diamond (EPO) |
| | E21.106 | Doping during the epitaxial deposition (EPO) |
| | E21.107 | Deposition of diamond (EPO) |
| | E21.108 | Epitaxial deposition of Group III-V compound (EPO) |
| | E21.114 | Using liquid deposition (EPO) |
| | E21.115 | Epitaxial deposition of Group IV elements, e.g., Si, Ge, C (EPO) |
| | E21.116 | Deposition on a semiconductor substrate which is different from the semiconductor material being deposited, i.e., formation of heterojunction (EPO) |
| | E21.117 | Epitaxial deposition of Group III-V compound (EPO) |
| | E21.119 | Characterized by the substrate (EPO) |
| | E21.12 | Characterized by the post-treatment used to control the interface betw een substrate and epitaxial layer, e.g., ion implantation followed by annealing (EPO) |
| | E21.121 | Substrate is crystalline insulating material, e.g., sapphire (EPO) |
| | E21.122 | Bonding of semiconductor wafer to insulating substrate or to semic onducting substrate using an intermediate insulating layer (EPO) |
| | E21.123 | Substrate is crystalline semiconductor material, e.g., lattice adaptation, heteroepitaxy (EPO) |
| | E21.124 | Heteroepitaxy (EPO) |
| | E21.125 | Defect and dislocati on suppression due to lattice mismatch, e.g., lattice adaptation (EPO) |
| | E21.126 | Group III-V compound on dissimilar Group III-V compound (EPO) |
| | E21.127 | Group III-V compound on Si or Ge (EPO) |
| | E21.128 | Carbon on a noncarbon semiconductor substrate (EPO) |
| | E21.129 | Group IVA, e.g., Si, C, Ge on Group IVB, e.g., Ti, Zr (EPO) |
| | E21.13 | The substrate is crystalline conducting material, e.g., metallic silicide (EPO) |
| | E21.131 | Selective epilaxial growth, e.g., simultaneous deposition of mono- and non-mono semiconductor material (EPO) |
| | E21.136 | From the substrate during epitaxy, e.g., autodoping; preventing or using autodoping (EPO) |
| | E21.137 | To control carrier lifetime, i.e., deep level dopant (EPO) |
| | E21.139 | Lithium-drift (EPO) |
| | E21.14 | Diffusion source (EPO) |
| | E21.141 | Using diffusion into or out of a solid from or into a gaseous phase (EPO) |
| | E21.144 | Using diffusion into or out of a s olid from or into a solid phase, e.g., a doped oxide layer (EPO) |
| | E21.145 | Diffusion into or out of Group IV semiconductor (EPO) |
| | E21.146 | Using predeposition of impurities into the semiconductor surface, e.g., from gaseous phase (EPO) |
| | E21.148 | From or through or into an applied layer, e.g., photoresist, nitride (EPO) |
| | E21.152 | Diffusion into or out of Group III-V compound (EPO) |
| | E21.153 | Using diffusion into or out of a solid from or into a liquid phase, e.g., alloy diffusion process (EPO) |
| | E21.154 | Alloying of impurity material, e.g., doping material, electrode material, with a semiconductor body (EPO) |
| | E21.155 | Alloying of doping material with Group III-V compound (EPO) |
| | E21.156 | Alloying of electrode material (EPO) |
| | E21.158 | Manufacture of electrode on semiconductor body using process other than by epitaxial growth, diffusion of impurities, alloying of impurity materials, or radiation bombardment (EPO) |
| | E21.159 | Deposition of conductive or insulating material for electrode conducting electric current (EPO) |
| | E21.16 | From a gas or vapor, e.g., condensation (EPO) |
| | E21.161 | Of conductive layer (EPO) |
| | E21.162 | On semiconductor body comprising Group IV element (EPO) |
| | E21.163 |  Deposition of Schottky electrode (EPO) |
| | E21.164 | O layer comprising silicide (EPO) |
| | E21.165 | Conductive layer comprising silicide (EPO) |
| | E21.166 | Conductive layer comprising semiconducting material (EPO) |
| | E21.168 | Conductive layer comprising transition metal, e.g., Ti, W, Mo (EPO) |
| | E21.169 | By physical means, e.g., sputtering, evaporation (EPO) |
| | E21.17 | By chemical means, e.g., CVD, LPCVD, PECVD, laser CVD (EPO) |
| | E21.172 | On semiconductor body comprising Group III-V compound (EPO) |
| | E21.174 | From a liquid, e.g., electrolytic deposition (EPO) |
| | E21.176 | Manufacture or post-treatment of electrode having a capacitive structure, i.e., gate structure for field-effect device (EPO) |
| | E21.177 | MOS-gate structure (EPO) |
| | E21.178 | Joint-gate structure (EPO) |
| | E21.179 | Floating or plural gate structure (EPO) |
| | E21.18 | Gate structure with charge-trapping insulator (EPO) |
| | E21.181 | On semiconductor body not comprising Group IV element, e.g., Group III-V compound (EPO) |
| | E21.182 | On semiconductor body comprising Group IV element excluding non-elemental Si, e.g., Ge, C, diamond, silicon compound or compound, such as SiC or SiGe (EPO) |
| | E21.183 | For charge-coupled device (EPO) |
| | E21.184 | PN-homojunction gate structure (EPO) |
| | E21.186 | Schottky gate structure (EPO) |
| | E21.188 | Heterojunction gate structure (EPO) |
| | E21.19 | Making electrode structure comprising conductor-insulator-semiconductor, e.g., MIS gate (EPO) |
| | E21.191 | Insulator formed on silicon semiconductor body (EPO) |
| | E21.192 | Characterized by insulator (EPO) |
| | E21.195 | Characterized by conductor (EPO) |
| | E21.196 | Final conductor next to insulator having lateral composition or doping variation, or being formed laterally by more than one deposition step (EPO) |
| | E21.197 | Final conductor layer next to insulator being silicon e.g., polysilicon, with or without impurities (EPO) |
| | E21.201 | Conductor layer next to insulator is Si or Ge or C and their non-Si alloys (EPO) |
| | E21.202 | Conductor layer next to the insulator is single metal, e.g., Ta, W, Mo, Al (EPO) |
| | E21.203 | Conductor layer next to insulator is metallic silicide (Me Si) (EPO) |
| | E21.204 | Conductor layer next to insulator is non-MeSi composite or compound, e.g., TiN (EPO) |
| | E21.205 | Characterized by sectional shape, e.g., T-shape, inverted T, spacer (EPO) |
| | E21.207 | Insulator formed on nonelemental silicon semiconductor body, e.g., Ge, SiGe, SiGeC (EPO) |
| | E21.208 | Comprising layer having ferroelectric properties (EPO) |
| | E21.209 | Making electrode structure comprising conductor-insulator-conuctor-insulator-semiconductor, e.g., gate stack for non-volatile memory (EPO) |
| | E21.21 | Comprising charge trapping insulator (EPO) |
| | E21.211 | Treatment of semiconductor body using process other than deposition of semiconductor material on a substrate, diffusion or alloying of impurity material, or radiation treatment (EPO) |
| | E21.212 | Hydrogenation or deuterization, e.g., using atomic hydrogen or deuterium from a plasma (EPO) |
| | E21.214 | To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (EPO) |
| | E21.215 | Chemical or electrical treatment, e.g., electrolytic etching (EPO) |
| | E21.216 | Electrolytic etching (EPO) |
| | E21.218 | Plasma etching; reactive-ion etching (EPO) |
| | E21.219 | Chemical etching (EPO) |
| | E21.224 | Chemical cleaning (EPO) |
| | E21.225 | Cleaning diamond or graphite (EPO) |
| | E21.226 | Dry cleaning (EPO) |
| | E21.228 | Wet cleaning only (EPO) |
| | E21.229 | Combining dry and wet cleaning steps (EPO) |
| | E21.23 | With simultaneous mechanical treatment, e.g., chemical-mechanical polishing (EPO) |
| | E21.231 | Using mask (EPO) |
| | E21.232 | Characterized by their composition, e.g., multilayer masks, materials (EPO) |
| | E21.233 | Characterized by their size, orientation, disposition, behavior, shape, in horizontal or vertical plane (EPO) |
| | E21.234 | Characterized by their behavior during process, e.g., soluble mask, redeposited mask (EPO) |
| | E21.235 | Characterized by process involved to create mask, e.g., lift-off mask, sidewall, or to modify the mask, e.g., pre-treatment, post-treatment (EPO) |
| | E21.236 | Process specially adapted to improve resolution of mask (EPO) |
| | E21.237 | Mechanical treatment, e.g., grinding, polishing, cutting (EPO) |
| | E21.24 | To form insulating layer thereon, e.g., for masking or by using photolithographic technique (EPO) |
| | E21.241 | Post-treatment (EPO) |
| | E21.242 | Of organic layer (EPO) |
| | E21.243 | Planarization of insulating layer (EPO) |
| | E21.247 | Doping insulating layer (EPO) |
| | E21.249 | Etching insulating layer by chemical or physical means (EPO) |
| | E21.258 | Using masks (EPO) |
| | E21.259 | Organic layers, e.g., photoresist (EPO) |
| | E21.26 | Layer comprising organo-silicon compound (EPO) |
| | E21.264 | Layers comprising fluoro hydrocarbon compounds, e.g., polytetrafluoroethylene (EPO) |
| | E21.265 | By Langmuir-Blodgett technique (EPO) |
| | E21.266 | Inorganic layer (EPO) |
| | E21.267 | Composed of alternated layers or of mixtures of nitrides and oxides or of oxynitrides, e.g., formation of oxynitride by oxidation of nitride layer (EPO) |
| | E21.268 | Of silicon (EPO) |
| | E21.27 | Carbon layer, e.g., diamond-like layer (EPO) |
| | E21.271 | Composed of oxide or glassy oxide or oxide based glass (EPO) |
| | E21.272 | With perovskite structure (EPO) |
| | E21.273 | Deposition of porous oxide or porous glassy oxide or oxide based porous glass (EPO) |
| | E21.274 | Deposition from gas or vapor (EPO) |
| | E21.275 |  Deposition of boron or phosphorus doped silicon oxide, e.g., BSG, PSG, BPSG (EPO) |
| | E21.276 | Deposition of halogen doped silicon oxide, e.g., fluorine doped silicon oxide (EPO) |
| | E21.277 | Deposition of carbon doped silicon oxide, e.g., SiOC (EPO) |
| | E21.278 | Deposition of silicon oxide (EPO) |
| | E21.28 | Deposition of aluminum oxide (EPO) |
| | E21.282 | Formed by oxidation (EPO) |
| | E21.292 | Inorganic layer composed of nitride (EPO) |
| | E21.294 | Deposition/post-treatment of noninsulating, e.g., conductive - or resistive - layers on insulating layers (EPO) |
| | E21.295 | Deposition of layer comprising metal, e.g., metal, alloys, metal compounds (EPO) |
| | E21.297 | Deposition of semiconductive layer, e.g., poly - or amorphous silicon layer (EPO) |
| | E21.298 | Deposition of superconductive layer (EPO) |
| | E21.299 | Deposition of conductive or semi-conductive organic layer (EPO) |
| | E21.3 | Post treatment (EPO) |
| | E21.301 | Oxidation of silicon-containing layer (EPO) |
| | E21.302 | Nitriding of silicon-containing layer (EPO) |
| | E21.303 | Planarization (EPO) |
| | E21.305 | Physical or chemical etching of layer, e.g., to produce a patterned layer from pre-deposited extensive layer (EPO) |
| | E21.306 | By physical means only (EPO) |
| | E21.308 | By chemical means only (EPO) |
| | E21.314 | Using mask (EPO) |
| | E21.315 | Doping layer (EPO) |
| | E21.317 | To modify their internal properties, e.g., to produce internal imperfections (EPO) |
| | E21.318 | Of silicon body, e.g., for gettering (EPO) |
| | E21.319 | Using cavities formed by inert gas ion implantation, e.g., hydrogen, noble gas (EPO) |
| | E21.32 | Of silicon on insulator (SOI) (EPO) |
| | E21.321 | Thermally inducing defects using oxygen present in silicon body for intrinsic gettering (EPO) |
| | E21.322 | Of Group III-V compound, e.g., to make them semi-insulating (EPO) |
| | E21.323 | Of diamond body (EPO) |
| | E21.324 | Thermal treatment for modifying the properties of semiconductor body, e.g., annealing, sintering (EPO) |
| | E21.325 | For the formation of PN junction without ad dition of impurities (EPO) |
| | E21.326 | Of Group III-V compound (EPO) |
| | E21.327 | Application of electric current or field, e.g., for electroforming (EPO) |
| | E21.328 | Radiation treatment (EPO) |
| | E21.329 | Using natural radiation, e.g., alpha , beta or gamma radiation (EPO) |
| | E21.33 | To produce chemical element by transmutation (EPO) |
| | E21.331 | With high-energy radiation (EPO) |
| | E21.332 | For etching, e.g., sputter etching (EPO) |
| | E21.333 | For heating, e.g., electron beam heating (EPO) |
| | E21.334 | Producing ions for implantation (EPO) |
| | E21.335 | In Group IV semiconductor (EPO) |
| | E21.336 | Of electrically active species (EPO) |
| | E21.338 | Recoil-implantation (EPO) |
| | E21.339 | Of electrically inactive species in silicon to make buried insulating layer (EPO) |
| | E21.34 | In Group III-V compound (EPO) |
| | E21.341 | Of electrically active species (EPO) |
| | E21.343 | Characterized by the implantation of both electrically active and inactive species in the same semiconductor region to be doped (EPO) |
| | E21.344 | In diamond (EPO) |
| | E21.345 | Characterized by the angle between the ion beam and the crystal planes or the main crystal surface (EPO) |
| | E21.346 | Using mask (EPO) |
| | E21.347 | Using electromagnetic radiation, e.g., laser radiation (EPO) |
| | E21.35 | Multi-step process for manufacture of device of bipolar type, e.g., diodes, transistors, thyristors, resistors, capacitors) (EPO) |
| | E21.351 | Device comprising one or two electrodes, e.g., diode, resistor or capacitor with PN or Schottky junctions (EPO) |
| | E21.352 | Diode (EPO) |
| | E21.353 | Tunnel diode (EPO) |
| | E21.354 | Transit time diode, e.g., IMPATT, TRAPATT diode (EPO) |
| | E21.355 | Break-down diode, e.g., Zener diode, avalanche diode (EPO) |
| | E21.358 | Rectifier diode (EPO) |
| | E21.359 | Schottky diode (EPO) |
| | E21.36 | Planar diode (EPO) |
| | E21.361 | Multi-layer diode, e.g., PNPN or NPNP diode (EPO) |
| | E21.362 | Gat ed-diode structure, e.g., SITh, FCTh, FCD (EPO) |
| | E21.363 | Resistor with PN junction (EPO) |
| | E21.364 | Capacitor with PN - or Schottky junction, e.g., varactor (EPO) |
| | E21.365 | Active layer is Group III-V compound (EPO) |
| | E21.369 | Device comprising three or more electrodes (EPO) |
| | E21.37 | Transistor (EPO) |
| | E21.371 | Heterojunction transistor (EPO) |
| | E21.372 | Bipolar thin film transistor (EPO) |
| | E21.373 | Lateral transistor (EPO) |
| | E21.374 | Schottky transistor (EPO) |
| | E21.375 | Silicon vertical transistor (EPO) |
| | E21.376 | Planar transistor (EPO) |
| | E21.377 | Mesa-planar transistor (EPO) |
| | E21.378 | Inverse transistor (EPO) |
| | E21.38 | Where main current goes through whole of silicon substrate, e.g., power bipolar transistor (EPO) |
| | E21.382 | Field-effect controlled bipolar-type transi stor, e.g., insulated gate bipolar transistor (IGBT) (EPO) |
| | E21.386 | Active layer, e.g., base, is Group III-V compound (EPO) |
| | E21.388 | Thyristor (EPO) |
| | E21.394 | Multi-step process for the manufacture of unipolar device (EPO) |
| | E21.396 | Metal-insulator-semiconductor capacitor, e.g., trench capacitor (EPO) |
| | E21.398 | Active layer is Group III-V compound (EPO) |
| | E21.4 | Field-effect transistor (EPO) |
| | E21.401 | Using static field induced region, e.g., SIT, PBT (EPO) |
| | E21.403 | With heterojunction interface channel or gate, e.g., HFET, HIGFET, SISFET, HJFET, HEMT (EPO) |
| | E21.405 | Active layer is Group III-V compound, e.g., III-V velocity modulation transistor (VMT), NERFET (EPO) |
| | E21.406 | Using static field induced region, e.g., SIT, PBT (EPO) |
| | E21.407 | With an heterojunction interface channel or gate, e.g., HFET, HIGFET, SI SFET, HJFET, HEMT (EPO) |
| | E21.409 | With an insulated gate (EPO) |
| | E21.41 | Vertical transistor (EPO) |
| | E21.411 | Thin film unipolar transistor (EPO) |
| | E21.412 | Amorphous silicon or polysilicon transistor (EPO) |
| | E21.413 | Lateral single gate single channel transistor with noninverted structure, i.e., channel layer is formed before gate (EPO) |
| | E21.414 | Lateral single gate single channel transistor with inverted structure, i.e., channel layer is formed after gate (EPO) |
| | E21.415 | Monocrystalline silicon transistor on insulating substrate, e.g., quartz substrate (EPO) |
| | E21.417 | With channel containing layer, e.g., p-base, fo rmed in or on drain region, e.g., DMOS transistor (EPO) |
| | E21.421 | With multiple gate, one gate having MOS structure and others having same or a different structure, i.e., non MOS, e.g., JFET gate (EPO) |
| | E21.422 | With floating gate (EPO) |
| | E21.423 | With charge trapping gate insulator, e.g., MNOS transistor (EPO) |
| | E21.424 | Lateral single gate silicon transistor (EPO) |
| | E21.425 | With source or drain region formed by Schottky barrier or conductor-insulator-semiconductor structure (EPO) |
| | E21.426 | With single crystalline channel formed on the silicon substrate after insulating device isolation (EPO) |
| | E21.427 | With asymmetry in channel direction, e.g., high-voltage lateral transistor with channel containing layer, e.g., p-base (EPO) |
| | E21.428 | With a recessed gate, e.g., lateral U-MOS (EPO) |
| | E21.429 | Using etching to form recess at gate location (EPO) |
| | E21.43 | Recessing gate by adding semiconductor material at source (S) or drain (D) location, e.g., transist or with elevated single crystal S and D (EPO) |
| | E21.431 | With source and drain recessed by etching or recessed and refi lled (EPO) |
| | E21.432 | With source and drain contacts formation strictly before final gate formation, e.g., contact first technology (EPO) |
| | E21.433 | Where the source and drain or source and drain extensions are self-aligned to sides of gate (EPO) |
| | E21.436 | Gate comprising layer with ferroelectric properties (EPO) |
| | E21.437 | With lightly doped drain selectively formed at side of gate (EPO) |
| | E21.438 | Using self-aligned silicidation, i.e., salicide (EPO) |
| | E21.44 | Using self-aligned selective metal deposition simultaneously on gate and on source or drain (EPO) |
| | E21.441 | Active layer is Group III-V compound (EPO) |
| | E21.442 | With gate at side of channel (EPO) |
| | E21.443 | Using self-aligned punch through stopper or threshold implant under gate region (EPO) |
| | E21.444 | Using dummy gate wherein at least part of final gate is self-aligned to dummy gate (EPO) |
| | E21.445 | With PN junction or heterojunction gate (EPO) |
| | E21.446 | With PN homojunction gate (EPO) |
| | E21.448 | With heterojunction gate (EPO) |
| | E21.449 | Active layer is Group III-V compound (EPO) |
| | E21.45 | With Schottky gate, e.g., MESFET (EPO) |
| | E21.451 | Active layer being Group III-V compound (EPO) |
| | E21.452 | Lateral single-gate transistors (EPO) |
| | E21.453 | Process wherein final gate is made after formation of source and drain regions in active layer, e.g., dummy-gate process (EPO) |
| | E21.454 | Process wherein final gate is made before formation, e.g., activation anneal, of source and drain regions in active layer (EPO) |
| | E21.455 | Lateral transistor with two or more independen t gates (EPO) |
| | E21.456 | Charge transfer device (EPO) |
| | E21.459 | Device having semiconductor body other than carbon, Si, Ge, SiC, Se, Te, Cu 2 O, CuI, and Group III-V compounds with or without impurities, e.g., doping materials (EPO) |
| | E21.46 | Multistep process (EPO) |
| | E21.461 | Deposition of semiconductor material on substrate, e.g., epitaxial growth (EPO) |
| | E21.462 | Using physical deposition, e.g., vacuum deposition, sputtering (EPO) |
| | E21.463 | Using reduction or decomposition of gaseous compound yielding solid condensate, i.e., chemical deposition (EPO) |
| | E21.464 | Using liquid deposition (EPO) |
| | E21.466 | Diffusion of impurity material, e.g., dopant, electrode material, into or out of semiconductor body, or between semiconductor regions (EPO) |
| | E21.467 | Using diffusion into or out of solid from or into gaseous phase (EPO) |
| | E21.468 | Using diffusion into or out of solid from or into solid phase, e.g., doped oxide layer (EPO) |
| | E21.469 | Using diffusion into or out of solid from or into liquid phase, e.g., alloy diffusion process (EPO) |
| | E21.47 | Alloying of impurity material, e.g., dopant, electrode material, with semiconductor body (EPO) |
| | E21.471 | Radiation treatment (EPO) |
| | E21.476 | Manufacture of electrodes on semiconductor bodies using processes or apparatus other than epitaxial growth, e.g., coating, diffusion, or alloying, or radiation treatment (EPO) |
| | E21.477 | Deposition of conductive or insulating materials for electrode (EPO) |
| | E21.478 | From gas or vapor, e.g., condensation (EPO) |
| | E21.479 | From liquid, e.g., electrolytic deposition (EPO) |
| | E21.48 | Involving application of pressure, e.g., thermo compression bonding (EPO) |
| | E21.481 | Including application of mechanical vibration, e.g., ultrasonic vibration (EPO) |
| | E21.482 | Treatment of semiconductor body using process other than electromagnetic radiation (EPO) |
| | E21.483 | To change their surface-physical characteristics or shape, e.g., etching, polishing, cutting (EPO) |
| | E21.484 | Mechanical treatment, e.g., grinding, ultrasonic treatment (EPO) |
| | E21.485 | Chemical or electrical treatment, e.g., electrolytic etching (EPO) |
| | E21.487 | To form insulating layer thereon, e.g., for masking or by using photolithographic techniques; post treatment of these layers (EPO) |
| | E21.488 | Using mask (EPO) |
| | E21.489 | Post treatment of insulating layer (EPO) |
| | E21.492 | Organic layer, e.g., photoresist (EPO) |
| | E21.493 | Inorganic layer (EPO) |
| | E21.495 | Deposition of noninsulating, e.g., conductive -, resistive -, layer on insulating layer (EPO) |
| | E21.497 | Thermal treatment for modifying property of semiconductor body, e.g., annealing, sintering (EPO) |
| | E21.498 | Application of electric current or fields, e.g., for electroforming (EPO) |
| | E21.499 | Assembling semiconductor devices, e.g., packaging , including mounting, encapsulating, or treatment of packaged semiconductor (EPO) |
| | E21.5 | Mounting semiconductor bodies in container (EPO) |
| | E21.501 | Providing fillings in container, e.g., gas fillings (EPO) |
| | E21.502 | Encapsulation, e.g., encapsulation layer, coating (EPO) |
| | E21.503 | Encapsulation of active face of flip chip device, e.g., under filling or under encapsulation of flip-chip, encapsulation perform on chip or mounting substrate (EPO) |
| | E21.504 | Moulds (EPO) |
| | E21.505 | Insulative mounting semiconductor device on support (EPO) |
| | E21.506 | Attaching or detaching leads or other conductive members, to be used for carrying current to or from device in operation (EPO) |
| | E21.507 | Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (EPO) |
| | E21.509 | Involving soldering or alloying process, e.g., soldering wires (EPO) |
| | E21.51 | Mounting on metallic conductive member (EPO) |
| | E21.511 | Mounting on insulating member provided with metallic leads, e.g., flip-chip mounting, conductive die mounting (EPO) |
| | E21.513 | Mounting on semiconductor conductive member (EPO) |
| | E21.514 | Involving use of conductive adhesive (EPO) |
| | E21.515 | Involving use of mechanical auxiliary part without use of alloying or soldering process, e.g., pressure contacts (EPO) |
| | E21.516 | Involving automation techniques using film carriers (EPO) |
| | E21.517 | Involving use of electron or laser beam (EPO) |
| | E21.518 | Involving application of mechanical vibration, e.g., ultrasonic vibration (EPO) |
| | E21.519 | Involving application of pressure, e.g., thermo-compression bonding (EPO) |
| | E21.52 | Devices having no potential-jump barrier or surface barrier (EPO) |
| | E21.521 | Testing or measuring during manufacture or treatment or reliability measurement, i.e., testing of parts followed by no processing which modifies parts as such (EPO) |
| | E21.522 | Structural arrangement (EPO) |
| | E21.523 | Additional lead-in metallization on device, e.g., additional pads or lands, lines in scribe line, sacrificed conductors, sacrificed frames (EPO) |
| | E21.525 | Procedures, i.e., sequence of activities consisting of plurality of measurement and correction, marking or sorting steps (EPO) |
| | E21.526 | Connection or disconnection of subentities or redundant parts of device in response to measurement, e.g., wafer scale, memory devices (EPO) |
| | E21.527 | Optical enhancement of defects or not directly visible states, e.g., selective electrolytic deposition, bubbles in liquids, light emission, color change (EPO) |
| | E21.528 | Acting in response to ongoing measurement without interruption of processing, e.g., endpoint detection, in-situ thickness measurement (EPO) |
| | E21.529 | Measuring as part of manufacturing process (EPO) |
| | E21.531 | For electrical parameters, e.g., resistance, deep-levels, CV, diffusions by electrical means (EPO) |
| | E21.533 | Of thick- or thin-film circuits or parts thereof (EPO) |
| | E21.534 | Of thick-film circuits or parts thereof (EPO) |
| | E21.535 | Of thin-film circuits or parts thereof (EPO) |
| | E21.536 | Manufacture of specific parts of devices (EPO) |
| | E21.537 | Making of localized buried regions, e.g., buried collector layer, internal connection, substrate contacts (EPO) |
| | E21.538 | Making of internal connections, substrate contacts (EPO) |
| | E21.539 | For Group III-V compound semiconductor integrated circuits (EPO) |
| | E21.54 | Making of isolation regions between components (EPO) |
| | E21.541 | Between components manufactured in active substrate comprising SiC compound semiconductor (EPO) |
| | E21.542 | Between components manufactured in active substrate comprising Group III-V compound semiconductor (EPO) |
| | E21.543 | Between components manufactured in active substrate comprising Group II-VI compound semiconductor (EPO) |
| | E21.544 | PN junction isolation (EPO) |
| | E21.545 | Dielectric regions, e.g., EPIC dielectric isolation, LOCOS; trench refilling techniques, SOI technology, use of channel stoppers (EPO) |
| | E21.546 | Using trench refilling with dielectric materials (EPO) |
| | E21.547 | Dielectric material being obtained by full chemical transformation of nondielectric materials, such as polycrystalline silicon, metals (EPO) |
| | E21.548 | Concurrent filling of plurality of trenches having different trench shape or dimension, e.g., rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches (EPO) |
| | E21.549 | Of trenches having shape other than rectangular or V shape, e.g., rounded corners, oblique or rounded trench walls (EPO) |
| | E21.55 | Trench shape altered by local oxidation of silicon process step, e.g., trench corner rounding by LOCOS (EPO) |
| | E21.551 | Introducing impurities in trench side or bottom walls, e.g., for forming channel stoppers or alter isolation behavior (EPO) |
| | E21.552 | Using local oxidation of silicon, e.g., LOCOS, SWAMI, SILO (EPO) |
| | E21.553 | In region recessed from surface, e.g., in recess, groove, tub or trench region (EPO) |
| | E21.554 | Using auxiliary pillars in recessed region, e.g., to form LOCOS over extended areas (EPO) |
| | E21.555 | Recessed region having shape other than rectangular, e.g., rounded or oblique shape (EPO) |
| | E21.556 | Introducing electrical inactive or active impurities in local oxidation region, e.g., to alter LOCOS oxide growth characteristics or for additional isolation purpose (EPO) |
| | E21.557 | Introducing electrical active impurities in local oxidation region solely for forming channel stoppers (EPO) |
| | E21.559 | With plurality of successive local oxidation steps (EPO) |
| | E21.56 | Dielectric isolation using EPIC technique, i.e., epitaxial passivated integrated circuit (EPO) |
| | E21.561 | Using semiconductor or insulator technology, i.e., SOI technology (EPO) |
| | E21.562 | Using selective deposition of single crystal silicon, e.g., Selective Epitaxial Growth (SEG) (EPO) |
| | E21.563 | Using silicon implanted buried insulating layers, e.g., oxide layers, i.e., SIMOX technique (EPO) |
| | E21.565 | Using full isolation by porous oxide silicon, i.e., FIPOS technique (EPO) |
| | E21.566 | Using lateral overgrowth technique, i.e., ELO techniques (EPO) |
| | E21.567 | Using bonding technique (EPO) |
| | E21.571 | Using selective deposition of single crystal silicon, i.e., SEG technique (EPO) |
| | E21.572 | Polycrystalline semiconductor regions (EPO) |
| | E21.573 | Air gaps (EPO) |
| | E21.574 | Isolation by field effect (EPO) |
| | E21.575 | Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (EPO) |
| | E21.576 | Characterized by formation and post treatment of dielectrics, e.g., planarizing (EPO) |
| | E21.577 | By forming via holes (EPO) |
| | E21.58 | Planarizing dielectric (EPO) |
| | E21.581 | Dielectric comprising air gaps (EPO) |
| | E21.582 | Characterized by formation and post treatment of conductors, e.g., patterning (EPO) |
| | E21.583 | Planarization; smoothing (EPO) |
| | E21.584 | Barrier, adhesion or liner layer (EPO) |
| | E21.585 | Filling of holes, grooves, vias or trenches with conductive material (EPO) |
| | E21.586 | By selective deposition of conductive material in vias, e.g., selective chemical vapor deposition on semiconductor material, plating (EPO) |
| | E21.587 | By deposition over sacrificial masking layer, e.g., lift-off (EPO) |
| | E21.588 | Reflowing or applying pressure to fill contact hole, e.g., to remove voids (EPO) |
| | E21.589 | By forming conductive members before deposition of protective insulating material, e.g., pillars, studs (EPO) |
| | E21.59 | Local interconnects; local pads (EPO) |
| | E21.591 | Modifying pattern or conductivity of conductive members, e.g., formation of alloys, reduction of contact resistances (EPO) |
| | E21.597 | Formed through semiconductor substrate (EPO) |
| | E21.598 | Manufacture or treatment of devices consisting of plurality of solid-state components or integrated circuits formed in, or on, common substrate (EPO) |
| | E21.599 | With subsequent division of substrate into plural individual devices (EPO) |
| | E21.6 | Involving separation of active layers from substrate (EPO) |
| | E21.602 | To produce devices each consisting of plurality of components, e.g., integrated circuits (EPO) |
| | E21.603 | Substrate is semiconductor, using combination of semiconductor substrates, e.g., diamond, SiC, Si, Group III-V compound, and/or Group II-VI compound semiconductor substrates (EPO) |
| | E21.604 | Substrate is semiconductor, using diamond technology (EPO) |
| | E21.605 | Substrate is semiconductor, using SiC technology (EPO) |
| | E21.606 | Substrate being semiconductor, using silicon technology (EPO) |
| | E21.607 | Substrate being semiconductor, using silicon technology (EPO) |
| | E21.608 | Bipolar technology (EPO) |
| | E21.609 | Comprising combination of vertical and lateral transistors (EPO) |
| | E21.61 | Comprising merged transistor logic or integrated injection logic (EPO) |
| | E21.611 | Complementary devices, e.g., complementary transistors (EPO) |
| | E21.613 | Memory structures (EPO) |
| | E21.614 | Three-dimensional integrated circuits stacked in different levels (EPO) |
| | E21.615 | Field-effect technology (EPO) |
| | E21.616 | MIS technology (EPO) |
| | E21.617 | Combination of charge coupled devices, i.e., CCD or BBD (EPO) |
| | E21.618 | With particular manufacturing method of channel, e.g., channel implants, halo or pocket implants, or channel materials (EPO) |
| | E21.619 | With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO) |
| | E21.62 | Manufacturing common source or drain regions between plurality of conductor-insulator-semiconductor structures (EPO) |
| | E21.621 | With particular manufacturing method of gate conductor, e.g., particular materials, shapes (EPO) |
| | E21.622 | Silicided or salicided gate conductors (EPO) |
| | E21.623 | Gate conductors with different gate conductor materials or different gate conductor implants, e.g., dual gate structures (EPO) |
| | E21.624 | Gate conductors with different shapes, lengths or dimensions (EPO) |
| | E21.626 | With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (EPO) |
| | E21.627 | Interconnection or wiring or contact manufacturing related aspects (EPO) |
| | E21.628 | Isolation region manufacturing related aspects, e.g., to avoid interaction of isolation region with adjacent structure (EPO) |
| | E21.629 | With particular manufacturing method of vertical transistor structures, i.e., with channel vertical to substrate surface (EPO) |
| | E21.63 | With particular manufacturing method of wells or tubs, e.g., twin tubs, high energy well implants, buried implanted layers for lateral isolation (BILLI) (EPO) |
| | E21.631 | Combination of enhancement and depletion transistors (EPO) |
| | E21.632 | Complementary field-effect transistors, e.g., CMOS (EPO) |
| | E21.633 | With particular manufacturing method of channel, e.g., channel implants, halo or pocket implants, or channel materials (EPO) |
| | E21.634 | With particular manufacturing method of source or drain, e.g., specific S or D implants or silicided S or D structures or raised S or D structures (EPO) |
| | E21.635 | With particular manufacturing method of gate conductor, e.g., particular materials, shapes (EPO) |
| | E21.636 | Silicided or salicided gate conductors (EPO) |
| | E21.637 | Gate conductors with different gate conductor materials or different gate conductor implants, e.g., dual gate structures (EPO) |
| | E21.638 | Gate conductors with different shapes, lengths or dimensions (EPO) |
| | E21.64 | With particular manufacturing method of gate sidewall spacers, e.g., double spacers, particular spacer material or shape (EPO) |
| | E21.641 | Interconnection or wiring or contact manufacturing related aspects (EPO) |
| | E21.642 | Isolation region manufacturing related aspects, e.g., to avoid interaction of isolation region with adjacent structure (EPO) |
| | E21.643 | With particular manufacturing method of vertical transistor structures, i.e., with channel vertical to substrate surface (EPO) |
| | E21.644 | With particular manufacturing method of wells or tubs, e.g., twin tubs, high energy well implants, buried implanted layers for lateral isolation (BILLI) (EPO) |
| | E21.645 | Memory structures (EPO) |
| | E21.646 | Dynamic random access memory structures (DRAM) (EPO) |
| | E21.647 | Characterized by type of capacitor (EPO) |
| | E21.648 | Capacitor stacked over transfer transis tor (EPO) |
| | E21.649 |  Making connection between transistor and capacitor, e.g., plug (EPO) |
| | E21.65 | Capacitor extending under transfer transistor area (EPO) |
| | E21.651 | Capacitor in U- or V-shaped trench in substrate (EPO) |
| | E21.654 | Characterized by type of transistor; manufacturing of transistor (EPO) |
| | E21.656 | Characterized by data lines (EPO) |
| | E21.66 | Simultaneous fabrication of periphery and memory cells (EPO) |
| | E21.661 | Static random access memory structures (SRAM) (EPO) |
| | E21.662 | Read-only memory structures (ROM), i.e., nonvolatile memory structures (EPO) |
| | E21.663 | Ferroelectric nonvolatile memory structures (EPO) |
| | E21.665 | Magnetic nonvolatile memory structures, e.g., MRAM (EPO) |
| | E21.666 | PROM (EPO) |
| | E21.667 | ROM only (EPO) |
| | E21.668 | With source and drain on same level, e.g., lateral channel (EPO) |
| | E21.669 |  Source or drain contact programmed (EPO) |
| | E21.67 | Gate contact programmed (EPO) |
| | E21.671 | Doping programmed, e.g., mask ROM (EPO) |
| | E21.674 | Gate programmed, e.g., different gate material or no gate (EPO) |
| | E21.675 | Gate dielectric programmed, e.g., different thickness (EPO) |
| | E21.676 | With source and drain on different levels, e.g., vertical channel (EPO) |
| | E21.677 | With FETs on different levels, e.g., 3D ROM (EPO) |
| | E21.678 | Simultaneous fabrication of periphery and memory cells (EPO) |
| | E21.679 | Charge trapping insulator nonvolatile memory structures (EPO) |
| | E21.68 | Electrically programmable (EPROM), i.e., floating gate memory structures (EPO) |
| | E21.681 | With conductive layer as control gate (EPO) |
| | E21.682 | With source and drain on same level and without cell select transistor (EPO) |
| | E21.683 |  Simultaneous fabrication of periphery and memory cells (EPO) |
| | E21.684 |  Including one type of peripheral FET (EPO) |
| | E21.685 |  Control gate layer used for peripheral FET (EPO) |
| | E21.686 | Intergate dielectric layer used for peripheral FET (EPO) |
| | E21.687 | Floating gate layer used for peripheral FET (EPO) |
| | E21.688 | Floating gate dielectric layer used for peripheral FET (EPO) |
| | E21.689 | Including different types of peripheral FETs (EPO) |
| | E21.69 | With source and drain on same level and with cell select transistor (EPO) |
| | E21.692 | With source and drain on different levels, e.g., sloping channel (EPO) |
| | E21.694 | With doped region as control gate (EPO) |
| | E21.695 | Combination of bipolar and field-effect technologies (EPO) |
| | E21.697 | Substrate is Group III-V semiconductor (EPO) |
| | E21.698 | Substrate is Group II-VI semiconductor (EPO) |
| | E21.699 | Substrate is semiconductor other than diamond, SiC, Si, Group III-V compound, or Group II-VI compound (EPO) |
| | E21.7 | Substrate is nonsemiconductor body, e.g., insulating body (EPO) |
| | E21.705 | Assembly of devices consisting of solid-state components formed in or on a common substrate; assembly of integrated circuit devices (EPO) |
| CROSS-REFERENCE ART COLLECTIONS | ||
| | 900 | MOSFET TYPE GATE SIDEWALL INSULATING SPACER |
| | 901 | MOSFET SUBSTRATE BIAS |
| | 902 | FET WITH METAL SOURCE REGION |
| | 903 | FET CONFIGURATION ADAPTED FOR USE AS STATIC MEMORY CELL |
| | 905 | PLURAL DRAM CELLS SHARE COMMON CONTACT OR COMMON TRENCH |
| | 906 | DRAM WITH CAPACITOR ELECTRODES USED FOR ACCESSING (E.G., BIT LINE IS CAPACITOR PLATE) |
| | 907 | FOLDED BIT LINE DRAM CONFIGURATION |
| | 908 | DRAM CONFIGURATION WITH TRANSISTORS AND CAPACITORS OF PAIRS OF CELLS ALONG A STRAIGHT LINE BETWEEN ADJACENT BIT LINES |
| | 909 | MACROCELL ARRAYS (E.G., GATE ARRAYS WITH VARIABLE SIZE OR CONFIGURATION OF CELLS) |
| | 910 | DIODE ARRAYS (E.G., DIODE READ-ONLY MEMORY ARRAY) |
| | 911 | LIGHT SENSITIVE ARRAY ADAPTED TO BE SCANNED BY ELECTRON BEAM (E.G.,VIDICON DEVICE) |
| | 912 | CHARGE TRANSFER DEVICE USING BOTH ELECTRON AND HOLE SIGNAL CARRIERS |
| | 913 | WITH MEANS TO ABSORB OR LOCALIZE UNWANTED IMPURITIES OR DEFECTS FROM SEMICONDUCTORS (E.G., HEAVY METAL GETTERING) |
| | 914 | POLYSILICON CONTAINING OXYGEN, NITROGEN, OR CARBON (E.G., SIPOS) |
| | 915 | WITH TITANIUM NITRIDE PORTION OR REGION |
| | 916 | NARROW BAND GAP SEMICONDUCTOR MATERIAL (<<1EV) |
| | 917 | PLURAL DOPANTS OF SAME CONDUCTIVITY TYPE IN SAME REGION |
| | 918 | LIGHT EMITTING REGENERATIVE SWITCHING DEVICE (E.G., LIGHT EMITTING SCR) ARRAYS, CIRCUITRY, ETC. |
| | 919 | ELEMENTS OF SIMILAR CONSTRUCTION CONNECTED IN SERIES OR PARALLEL TO AVERAGE OUT MANUFACTURING VARIATIONS IN CHARACTERISTICS |
| | 920 | CONDUCTOR LAYERS ON DIFFERENT LEVELS CONNECTED IN PARALLEL (E.G., TO REDUCE RESISTANCE) |
| | 921 | RADIATION HARDENED SEMICONDUCTOR DEVICE |
| | 922 | WITH MEANS TO PREVENT INSPECTION OF OR TAMPERING WITH AN INTEGRATED CIRCUIT (E.G., "SMART CARD", ANTI-TAMPER) |
| | 923 | WITH MEANS TO OPTIMIZE ELECTRICAL CONDUCTOR CURRENT CARRYING CAPACITY (E.G., PARTICULAR CONDUCTOR ASPECT RATIO) |
| | 924 | WITH PASSIVE DEVICE (E.G., CAPACITOR), OR BATTERY, AS INTEGRAL PART OF HOUSING OR HOUSING ELEMENT (E.G., CAP) |
| | 925 | BRIDGE RECTIFIER MODULE |
| | 926 | ELONGATED LEAD EXTENDING AXIALLY THROUGH ANOTHER ELONGATED LEAD |
| | 927 | DIFFERENT DOPING LEVELS IN DIFFERENT PARTS OF PN JUNCTION TO PRODUCE SHAPED DEPLETION LAYER |
| | 928 | WITH SHORTED PN OR SCHOTTKY JUNCTION OTHER THAN EMITTER JUNCTION |
| | 929 | PN JUNCTION ISOLATED INTEGRATED CIRCUIT WITH ISOLATION WALLS HAVING MINIMUM DOPANT CONCENTRATION AT INTERMEDIATE DEPTH IN EPITAXIAL LAYER (E.G., DIFFUSED FROM BOTH SURFACES OF EPITAXIAL LAYER) |
| | 930 | THERMOELECTRIC (E.G., PELTIER EFFECT) COOLING |
| FOREIGN ART COLLECTIONS | ||
| FOR000 | CLASS-RELATED FOREIGN DOCUMENTS |